ZHCSFY1F
December 2016 – April 2024
TDP158
PRODUCTION DATA
1
1
特性
2
应用
3
说明
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics, Power Supply
5.6
Electrical Characteristics, Differential Input
5.7
Electrical Characteristics, TMDS Differential Output
5.8
Electrical Characteristics, DDC, I2C, HPD, and ARC
5.9
Electrical Characteristics, TMDS Differential Output in DP-Mode
5.10
Switching Characteristics, TMDS
5.11
Switching Characteristics, HPD
5.12
Switching Characteristics, DDC and I2C
5.13
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Reset Implementation
7.3.2
Operation Timing
7.3.3
Lane Control
7.3.4
Swap
7.3.5
Main Link Inputs
7.3.6
Receiver Equalizer
7.3.7
Input Signal Detect Block
7.3.8
Transmitter Impedance Control
7.3.9
TMDS Outputs
7.3.10
Slew Rate Control
7.3.11
Pre-Emphasis
7.3.12
DP-Mode Description
7.4
Device Functional Modes
7.4.1
DDC Training for HDMI 2.0 Data Rate Monitor
7.4.2
DDC Functional Description
7.5
Register Maps
7.5.1
Local I2C Control BIT Access TAG Convention
7.5.2
BIT Access Tag Conventions
7.5.3
CSR Bit Field Definitions, DEVICE_ID (address = 00h≅07h)
7.5.4
CSR Bit Field Definitions, REV_ID (address = 08h )
7.5.5
CSR Bit Field Definitions – MISC CONTROL 09h (address = 09h)
7.5.6
CSR Bit Field Definitions – MISC CONTROL 0Ah (address = 0Ah)
7.5.7
CSR Bit Field Definitions – MISC CONTROL 0Bh (address = 0Bh)
7.5.8
CSR Bit Field Definitions – MISC CONTROL 0Ch (address = 0Ch)
7.5.9
CSR Bit Field Definitions, Equalization Control Register (address = 0Dh)
7.5.10
CSR Bit Field Definitions, POWER MODE STATUS (address = 20h)
7.5.11
CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 30h)
7.5.12
CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 31h)
7.5.13
CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 32h)
7.5.14
CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 33h)
7.5.15
CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 34h)
7.5.16
CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 35h)
7.5.17
CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Dh)
7.5.18
CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Eh)
7.5.19
CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Fh)
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Source Side
8.2.2.2
DDC Pull Up Resistors
8.2.3
Application Curves
8.2.4
Application with DDC Snoop
8.2.4.1
Source Side HDMI Application
8.2.5
9.1.2 Source Side HDMI /DP Application Using DP-Mode
8.3
Power Supply Recommendations
8.3.1
Power Management
8.3.2
Standby Power
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
接收文档更新通知
9.3
支持资源
9.4
Trademarks
9.5
静电放电警告
9.6
术语表
10
Revision History
11
Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
RSB|40
MPQF185C
散热焊盘机械数据 (封装 | 引脚)
RSB|40
QFND255H
订购信息
zhcsfy1f_oa
zhcsfy1f_pm
1
特性
交流耦合 TMDS 或
DisplayPort™
双模物理层输入到 HDMI2.0b TMDS 物理层输出,支持高达 6Gbps 的数据速率,兼容 HDMI2.0b 电气参数
支持 DisplayPort 双模标准版本 1.1
支持 4k 2k 60p 和高达 WUXGA 16 位色深或 1080p,刷新率更高
可编程固定接收器均衡器增益最高可达
15.5dB
全局或独立的高速通道控制、预加重和发送摆幅以及转换率控制
I
2
C 或引脚搭接可编程
可通过 I
2
C 配置为 DisplayPort 转接驱动器
主通道上全通道交换
低功耗
6Gbps 时的工作功耗为 -200mW,关断状态下的功耗为 -8mW
采用 40 引脚、0.4mm 间距、5mm x 5mm WQFN 封装,与 SN75DP159RSB 重计时器引脚兼容
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