米6体育平台手机版

ZHCSAH8B November 2012 – March 2022 TFP401A-Q1

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

PZP|100
- MPQF053D

散热焊盘机械数据 (封装 | 引脚)

PZP|100
- PPTD033I

订购信息

zhcsah8b_oa

6.8 Timing Requirements

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
t_ps	Analog input intra-pair (+ to –) differential skew ⁽²⁾			0.4	t_bit⁽¹⁾
t_ccs	Analog input inter-pair or channel-to-channel skew ⁽²⁾			1	t_pix⁽³⁾
t_ijit	Worst-case differential input-clock jitter tolerance⁽²⁾⁽⁴⁾		50		ps
t_f1	Fall time of data and control signals⁽⁵⁾⁽⁶⁾	ST = low, C_L = 5 pF		2.4	ns
t_f1	Fall time of data and control signals⁽⁵⁾⁽⁶⁾	ST = high, C_L = 10 pF		1.9	ns
t_r1	Rise time of data and control signals⁽⁵⁾⁽⁶⁾	ST = low, C_L = 5 pF		2.4	ns
t_r1	Rise time of data and control signals⁽⁵⁾⁽⁶⁾	ST = high, C_L = 10 pF		1.9	ns
t_r2	Rise time of ODCK clock⁽⁵⁾	ST = low, C_L = 5 pF		2.4	ns
t_r2	Rise time of ODCK clock⁽⁵⁾	ST = high, C_L = 10 pF		1.9	ns
t_f2	Fall time of ODCK clock⁽⁵⁾	ST = low, C_L = 5 pF		2.4	ns
t_f2	Fall time of ODCK clock⁽⁵⁾	ST = high, C_L = 10 pF		1.9	ns
t_su1	Setup time, data and control signal to falling edge of ODCK	1 pixel per clock, PIXS = low, OCK_INV = low	1.8		ns
		2 pixels per clock, PIXS = high, STAG = high, OCK_INV = low	3.8
		2 pixels and STAG, PIXS = high, STAG = low, OCK_INV = low	0.6
t_h1	Hold time, data and control signal to falling edge of ODCK	1 pixel per clock, PIXS = low, OCK_INV = low	0.6		ns
		2 pixels and STAG, PIXS = high, STAG = low, OCK_INV = low	2.5
		2 pixels per clock, PIXS = high, STAG = high, OCK_INV = low	2.9
t_su2	Setup time, data and control signal to rising edge of ODCK	1 pixels per clock, PIXS = low, OCK_INV = high	2.1		ns
		2 pixels per clock, PIXS = high, STAG = high, OCK_INV = high	4
		2 pixels and STAG, PIXS = high, STAG = low, OCK_INV = high	1.5
t_h2	Hold time, data and control signal to rising edge of ODCK	1 pixel per clock, PIXS = low, OCK_INV = high	0.3		ns
		2 pixels and STAG, PIXS = high, STAG = low, OCK_INV = high	2.4
		2 pixels per clock, PIXS = high, STAG = high, OCK_INV = high	2.1
t_pix	Pixel time⁽³⁾		6.06	40	ns

(1) t_bit is 1/10 the pixel time, t_pix.

(2) Specified by characterization.

(3) t_pix is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK, is equal to t_pix when in 1-pixel-per-clock mode or 2 t_pix when in 2-pixels-per-clock mode.

(4) Measured differentially at 50% crossing using ODCK output clock as trigger.

(5) Rise and fall times measured as time between 20% and 80% of signal amplitude.

(6) Data and control signals are QE[23:0], QO[23:0], DE, HSYNC, VSYNC. and CTL[3:1].

(7) Amount of time detected between DE transitions determines whether link is active or inactive. SCDT indicates link activity.