The TFP401A-Q1 device provides flexibility by offering various output driver features for use to optimize power consumption, ground bounce, and power-supply noise. The following sections outline the output driver features and their effects.

Output Driver Power Down (PDO = low): Pulling PDO low places all the output drivers, except CTL1 and SCDT, into a high-impedance state. One can tie the SCDT output, which indicates link-disabled or link-inactive, directly to the PDO input to disable the output drivers when the link is inactive or when the cable is disconnected. An internal pullup on the PDO pin defaults the TFP401A-Q1 device to the normal nonpower-down output-drive mode if left unconnected.

Drive Strength (ST = high for high drive strength, ST = low for low drive strength): The TFP401A-Q1 device allows for selectable output drive strength on the data, control, and ODCK outputs. See the DC Electrical Characteristics table for the values of I_OH and I_OL current drives for a given ST state. The high output-drive strength offers approximately two times the drive as the low output-drive strength.

Time-Staggered Pixel Output: This option works only in conjunction with the 2-pixels-per-clock mode (PIXS = high). Setting STAG = low time-staggers the even- and odd-pixel outputs so as to reduce the amount of instantaneous current surge from the power supply. Depending on the PCB layout and design, this can help reduce the amount of system ground bounce and power-supply noise. The time stagger is such that in 2-pixels-per-clock mode, the even pixel is delayed from the latching edge of ODCK by 0.25 t_cip. (t_cip is the period of ODCK. The ODCK period is 2 t_pix when in 2-pixels-per-clock mode.)

Depending on system constraints of output load, pixel rate, panel input architecture, and board cost, the TFP401A-Q1 drive-strength and staggered-pixel options allow flexibility to reduce system power-supply noise, ground bounce, and EMI.

Power Management: The TFP401A-Q1 device offers several system power-management features.

The output-driver power down (PDO = low) is an intermediate mode which offers several uses. During this mode, all output drivers except SCDT and CTL1 go into a high-impedance state while the rest of the device circuitry remains active.

Power down (PD = low) of the TFP401A-Q1 device is a complete power down in that it powers down the digital core, the analog circuitry, and output drivers. All output drivers go into a Hi-Z state. Of all the inputs, only PD remains active. The TFP401A-Q1 device does not respond to any digital or analog inputs until PD is pulled high.

Both PDO and PD have internal pullups, so if left unconnected they default the TFP401A-Q1 device to normal operating modes.

Sync Detect: The TFP401A-Q1 device offers an output, SCDT, to indicate link activity. The TFP401A-Q1 device monitors activity on DE to determine if the link is active. When 1 million (1e6) pixel clock periods pass without a transition on DE, the TFP401A-Q1 device considers the link inactive, and drives SCDT low. While SCDT is low, if two DE transitions are detected within 1600 pixel clock periods, the device considers the link active and pulls SCDT high.

A use of SCDT is to signal a system power management circuit to initiate a system power down when the device considers the link inactive. The SCDT can also be tied directly to the TFP401A-Q1 PDO input to power down the output drivers when the link is inactive. It is not recommended to use SCDT to drive the PD input, because once in complete power-down, the analog inputs are ignored and the SCDT state does not change. An external system power-management circuit to drive PD is preferred.