ZHCSAH8B November 2012 – March 2022 TFP401A-Q1
PRODUCTION DATA
The TFP401A-Q1 device provides system design flexibility and value by providing the system designer with configurable options or modes of operation to support varying system architectures. Table 7-2 outlines the various supportable panel modes, along with appropriate external control pin settings.
PANEL | PIXEL RATE | ODCK LATCH EDGE | ODCK | DFO | PIXS | OCK_INV |
---|---|---|---|---|---|---|
TFT or 16-bit DSTN | 1 pixel per clock | Falling | Free run | 0 | 0 | 0 |
TFT or 16-bit DSTN | 1 pixel per clock | Rising | Free run | 0 | 0 | 1 |
TFT | 2 pixels per clock | Falling | Free run | 0 | 1 | 0 |
TFT | 2 pixels per clock | Rising | Free run | 0 | 1 | 1 |
24-bit DSTN | 1 pixel per clock | Falling | Gated low | 1 | 0 | 0 |
None | 1 pixel per clock | Rising | Gated low | 1 | 0 | 1 |
24-bit DSTN | 2 pixels per clock | Falling | Gated low | 1 | 1 | 0 |
24-bit DSTN | 2 pixels per clock | Rising | Gated low | 1 | 1 | 1 |