ZHCSUT0D October   2001  – February 2024 TFP410

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 T.M.D.S. Pixel Data and Control Signal Encoding
      2. 6.3.2 Universal Graphics Controller Interface Voltage Signal Levels
      3. 6.3.3 Universal Graphics Controller Interface Clock Inputs
    4. 6.4 Device Functional Modes
      1. 6.4.1 Universal Graphics Controller Interface Modes
      2. 6.4.2 Data De-skew Feature
      3. 6.4.3 Hot Plug/Unplug (Auto Connect/Disconnect Detection)
      4. 6.4.4 Device Configuration and I2C RESET Description
      5. 6.4.5 DE Generator
    5. 6.5 Programming
      1. 6.5.1 I2C Interface
    6. 6.6 Register Maps
      1. 6.6.1  VEN_ID Register (Sub-Address = 01−00 ) [reset = 0x014C]
      2. 6.6.2  DEV_ID Register (Sub-Address = 03–02) [reset = 0x0410]
      3. 6.6.3  REV_ID Register (Sub-Address = 04) [reset = 0x00]
      4. 6.6.4  Reserved Register (Sub-Address = 07–05) [reset = 0x641400]
      5. 6.6.5  CTL_1_MODE (Sub-Address = 08) [reset = 0xBE]
      6. 6.6.6  CTL_2_MODE Register (Sub-Address = 09) [reset = 0x00]
      7. 6.6.7  CTL_3_MODE Register (Sub-Address = 0A) [reset = 0x80]
      8. 6.6.8  CFG Register (Sub-Address = 0B)
      9. 6.6.9  RESERVED Register (Sub-Address = 0E–0C) [reset = 0x97D0A9]
      10. 6.6.10 DE_DLY Register (Sub-Address = 32) [reset = 0x00]
      11. 6.6.11 DE_CTL Register (Sub-Address = 33) [reset = 0x00]
      12. 6.6.12 DE_TOP Register (Sub-Address = 34) [reset = 0x00]
      13. 6.6.13 DE_CNT Register (Sub-Address = 37–36) [reset = 0x0000]
      14. 6.6.14 DE_LIN Register (Sub-Address = 39–38) [reset = 0x0000]
      15. 6.6.15 H_RES Register (Sub-Address = 3B−3A)
      16. 6.6.16 V_RES Register (Sub-Address = 3D−3C)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Data and Control Signals
        2. 7.2.2.2 Configuration Options
        3. 7.2.2.3 Power Supplies Decoupling
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 DVDD
      2. 7.3.2 TVDD
      3. 7.3.3 PVDD
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Layer Stack
        2. 7.4.1.2 Routing High-Speed Differential Signal Traces (RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+)
        3. 7.4.1.3 DVI Connector
      2. 7.4.2 Layout Example
      3. 7.4.3 TI PowerPAD 64-Pin HTQFP Package
  9. 8 Device and Documentation Support
    1. 8.1 接收文档更新通知
    2. 8.2 支持资源
    3. 8.3 Trademarks
    4. 8.4 静电放电警告
    5. 8.5 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • PAP|64
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.4.1 Universal Graphics Controller Interface Modes

Table 6-1 is a tabular representation of the different modes for the universal graphics controller interface. The 12-bit mode is selected when BSEL=0 and the 24-bit mode when BSEL=1. The 12-bit mode uses dual-edge clocking and the 24-bit mode uses single-edge clocking. The EDGE input is used to control the latching edge in 24-bit mode, or the primary latching edge in 12-bit mode. When EDGE=1, the data input is latched on the rising edge of the input clock; and when EDGE=0, the data input is latched on the falling edge of the input clock. A fully differential input clock is available only in the low-swing mode. Single-ended clocking is not recommended in the low-swing mode as this decreases common-mode noise rejection.

Note that BSEL, DSEL, and EDGE are determined by register CTL_1_MODE when I2C is enabled (ISEL=1) and by input pins when I2C is disabled (ISEL=0).

Table 6-1 Universal Graphics Controller Interface Options (Tabular Representation)
VREFBSELEDGEDSELBUS WIDTHLATCH MODECLOCK EDGECLOCK MODE
0.55V − 0.9V00012-bitDual-edgeFallingDifferential(1)(2)
0.55V − 0.9V00112-bitDual-edgeFallingSingle-ended
0.55V – 0.9V01012-bitDual-edgeRisingDifferential(1)(2)
0.55V − 0.9V01112-bitDual-edgeRisingSingle-ended
0.55V – 0.9V10024-bitSingle-edgeFallingSingle-ended
0.55V – 0.9V10124-bitSingle-edgeFallingDifferential(1)(3)
0.55V – 0.9V11024-bitSingle-edgeRisingSingle-ended
0.55V – 0.9V11124-bitSingle-edgeRisingDifferential(1)(3)
DVDD00X12-bitDual-edgeFallingSingle-ended(4)
DVDD01X12-bitDual-edgeRisingSingle-ended(4)
DVDD10X24-bitSingle-edgeFallingSingle-ended(4)
DVDD11X24-bitSingle-edgeRisingSingle-ended(4)
(1) The differential clock input mode is only available in the low signal swing mode (that is, VREF ≤ 0.9V).
(2) The TFP410 does not support a 12-bit dual-clock, single-edge input clocking mode.
(3) The TFP410 does not support a 24-bit single-clock, dual-edge input clocking mode.
(4) In the high-swing mode (VREF = DVDD), DSEL is a don’t care; therefore, the device is always in the single-ended latch mode.
GUID-7CD7C1D2-176D-4F79-AD23-6E8A40BA805F-low.gifFigure 6-1 Universal Graphics Controller Interface Options for 12-Bit Mode (Graphical Representation)
GUID-FAFCEA05-9FA6-48BF-8906-CDC9A1B022BD-low.gifFigure 6-2 Universal Graphics Controller Interface Options for 24-Bit Mode (Graphical Representation)
Table 6-2 12-Bit Mode Data Mapping
PIN NAMEP0P1P2
P0LP0HP1LP1HP2LP2H
LOWHIGHLOWHIGHLOWHIGH
D11G0[3]R0[7]G1[3]R1[7]G2[3]R2[7]
D10G0[2]R0[6]G1[2]R1[6]G2[2]R2[6]
D9G0[1]R0[5]G1[1]R1[5]G2[1]R2[5]
D8G0[0]R0[4]G1[0]R1[4]G2[0]R2[4]
D7B0[7]R0[3]B1[7]R1[3]B2[7]R2[3]
D6B0[6]R0[2]B1[6]R1[2]B2[6]R2[2]
D5B0[5]R0[1]B1[5]R1[1]B2[5]R2[1]
D4B0[4]R0[0]B1[4]R1[0]B2[4]R2[0]
D3B0[3]G0[7]B1[3]G1[7]B2[3]G2[7]
D2B0[2]G0[6]B1[2]G1[6]B2[2]G2[6]
D1B0[1]G0[5]B1[1]G1[5]B2[1]G2[5]
D0B0[0]G0[4]B1[0]G1[4]B2[0]G2[4]
Table 6-3 24-Bit Mode Data Mapping
PIN NAMEP0P1P2PIN NAMEP0P1P2
D23R0[7]R1[7]R2[7]D11G0[3]G1[3]G2[3]
D22R0[6]R1[6]R2[6]D10G0[2]G1[2]G2[2]
D21R0[5]R1[5]R2[5]D9G0[1]G1[1]G2[1]
D20R0[4]R1[4]R2[4]D8G0[0]G1[0]G2[0]
D19R0[3]R1[3]R2[3]D7B0[7]B1[7]B2[7]
D18R0[2]R1[2]R2[2]D6B0[6]B1[6]B2[6]
D17R0[1]R1[1]R2[1]D5B0[5]B1[5]B2[5]
D16R0[0]R1[0]R2[0]D4B0[4]B1[4]B2[4]
D15G0[7]G1[7]G2[7]D3B0[3]B1[3]B2[3]
D14G0[6]G1[6]G2[6]D2B0[2]B1[2]B2[2]
D13G0[5]G1[5]G2[5]D1B0[1]B1[1]B2[1]
D12G0[4]G1[4]G2[4]D0B0[0]B1[0]B2[0]
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