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7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage	Supply, +V_CC – (–V_CC)		16.2	V
	Input/output	(–V_CC) – 0.5	(+V_CC) + 0.5
	Differential input voltage (IN+ – IN–)		±8
Current	Continuous input current (IN+, IN–, VMID_IN, VIN+, VIN–)⁽²⁾		±10	mA
Current	Continuous output current⁽²⁾		±30	mA
Temperature	Operating, T_A	–55	105	°C
	Junction, T_J	–45	150
	Storage, T_stg	–65	150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Long-term continuous current for electromigration limits.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
+V_CC	Positive supply voltage	4	6	7.9	V
–V_CC	Negative supply voltage	–4	–6	–7.9	V
T_A	Operating free-air temperature	–40	25	85	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		THS3217	UNIT
		RGV (VQFN)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	45	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	45	°C/W
R_θJB	Junction-to-board thermal resistance	22	°C/W
ψ_JT	Junction-to-top characterization parameter	1	°C/W
ψ_JB	Junction-to-board characterization parameter	22	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	4	°C/W

(1) Thermal impedance reported with backside thermal pad soldered to heat spreading plane. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics: D2S

at +V_CC = 6.0 V, –V_CC = –6.0 V, A_V = 2 V/V, 25-Ω source impedance, input common-mode voltage (V_IC) = 0.25 V, external OPS input selected (PATHSEL ≥ 1.3 V), V_REF = GND, R_LOAD = 100 Ω, and T_J ≈ 25˚C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT	TEST LEVEL ⁽¹⁾
AC PERFORMANCE (Power Stage Disabled: DISABLE pin ≥ 1.3 V) ⁽⁵⁾
	Small-signal bandwidth (SSBW)	V_OUT = 250 mV_PP, peaking < 1.0 dB		800		MHz	C
	Large-signal bandwidth (LSBW)	V_OUT = 2 V_PP		500		MHz	C
	Bandwidth for 0.2-dB flatness	V_OUT = 2 V_PP		250		MHz	C
	Slew rate⁽²⁾	V_OUT = 4-V step		2500		V/µs	C
	Over- and undershoot	Input t_r = 1 ns, V_OUT = 2-V step		6%			C
	Rise and fall time	Input t_r = 1 ns, V_OUT = 2-V step		1.2		ns	C
	Settling time to 0.1%	Input t_r = 1 ns, V_OUT = 2-V step		5		ns	C
	2nd-order harmonic distortion (HD2)	f = 20 MHz, V_OUT= 2 V_PP		–68		dBc	C
	3rd-order harmonic distortion (HD3)	f = 20 MHz, V_OUT= 2 V_PP		–86		dBc	C
	Output voltage noise	f > 200 kHz		18		nV/√Hz	C
	Input current noise (each input)	f > 200 kHz		2.0		pA/√Hz	C
	Output impedance	f = 20 MHz		0.8		Ω	C
DC PERFORMANCE ⁽⁵⁾
	Differential to single-ended gain	±100-mV output	1.975	2.0	2.025	V/V	A
	Differential to single-ended gain drift	T_J = –40°C to +125°C		–20	–24	ppm/°C	B
	VREF input pin gain	Differential inputs = 0 V, V_REF = ±100 mV	0.985	1.0	1.015	V/V	A
	VREF input pin gain drift	T_J = –40°C to +125°C		–70	–95	ppm/°C	B
	Output offset voltage	T_J = 25°C	–35	±8	35	mV	A
		T_J = 0°C to 70°C	–43		40	mV	B
		T_J = –40°C to +125°C	–54		47	mV	B
	Output offset voltage drift	T_J = –40°C to +125°C	-40	–115	–190	µV/°C	B
	Input bias current – each input⁽³⁾	T_J = 25°C	–4	±2	4	µA	A
		T_J = 0°C to 70°C	–4.2		4.2	µA	B
		T_J = –40°C to +125°C	–4.3		4.5	µA	B
	Input bias current drift	T_J = –40°C to +125°C	1	3	5	nA/°C	B
	Input offset current	T_J = 25°C	–400	±50	400	nA	A
		T_J = 0°C to 70°C	–700		940	nA	B
		T_J = –40°C to +125°C	–1180		1600	nA	B
	Input offset current drift	T_J = –40°C to +125°C	–12	±1	12	nA/°C	B
INPUTS⁽⁴⁾
	Common-mode input negative supply headroom	T_J = 25°C		1.8	1.9	V	A
	Common-mode input negative supply headroom	T_J = –40°C to +85°C			2.0	V	B
	Common-mode input positive supply headroom	T_J = 25°C		1.3	1.4	V	A
	Common-mode input positive supply headroom	T_J = –40°C to +125°C			1.5	V	B
	Common-mode rejection ratio (CMRR)	–1 V ≤ V_IC ≤ 3 V	47	55		dB	A
	Input impedance differential mode	V_CM = 0 V		50 \|\| 2.4		kΩ \|\| pF	C
	Input impedance common mode	V_CM = 0 V		90 \|\| 2.4		kΩ \|\| pF	C
OUTPUT⁽⁶⁾
	Output voltage headroom to either supply	T_J = 25°C	1.1	1.35	1.55	V	A
	Output voltage headroom to either supply	T_J = –40°C to +125°C				V	B
	Output current drive	T_J = 25°C, ±1.16 V_PP, R_LOAD = 20 Ω	50	70		mA	A
	DC Output Impedance	Load current = ±20 mA		0.2	0.45	Ω	A
POWER SUPPLY (D2S Stage + Midsupply Buffer Only; Output Power Stage Disabled: DISABLE pin ≥ 1.3 V)
	Bipolar-supply operating range		±4.0	±6.0	±7.9	V	A
	Single-supply operating range		8	12	15.8	V	B
	Supply current	±6-V supplies	31	34	36	mA	A
	Supply current temperature coefficient			7		µA/°C	C

(1) Test levels (all values set by characterization and simulation): (A) 100% tested at T_A≈ T_J≈ 25°C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information. DC limits tested with no self-heating. Add internal self heating to T_A for T_J.

(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (Vpeak / √2) × 2π × f_–3dB.

(3) Currents out of pin treated as a positive polarity.

(4) Applies to input pins 2 (IN+) and 3 (IN–).

(5) Output measured at pin 6.

(6) Output measured at pin 6.

7.6 Electrical Characteristics: OPS

at +V_CC = 6.0 V, –V_CC = –6.0 V, 25-Ω D2S source impedance, D2S input common-mode voltage (V_IC) = 0.25 V, V_REF = GND, R_F = 249 Ω⁽¹⁾, R_G = 162 Ω, A_V = 2.5 V/V, OPS R_LOAD = 100 Ω, OPS enabled (DISABLE ≤ 0.7 V or floated), external OPS input selected (PATHSEL ≥ 1.3 V), and T_J ≈ 25˚C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT	TEST LEVEL ⁽²⁾
AC PERFORMANCE ⁽⁴⁾
	Small-signal bandwidth (SSBW)	V_OUT = 100 mV_PP, peaking < 1.0 dB		950		MHz	C
	Large-signal bandwidth (LSBW)	V_OUT = 5 V_PP		500		MHz	C
	Bandwidth for 0.2-dB flatness	V_OUT = 5 V_PP		110		MHz	C
	Slew rate⁽³⁾	V_OUT = 5-V step		5500		V/µs	C
	Over- and undershoot	Input t_r = 1 ns, V_OUT = 5-V step		8%			C
	Rise and fall time	Input t_r = 1 ns, V_OUT = 5-V step		1.1		ns	C
	Settling time to 0.1%	Input t_r = 1 ns, V_OUT = 5-V step		5		ns	C
	2nd-order harmonic distortion (HD2)	f = 20 MHz, V_OUT= 5 V_PP		–69		dBc	C
	3rd-order harmonic distortion (HD3)	f = 20 MHz, V_OUT= 5 V_PP		–73		dBc	C
	Noninverting input voltage noise	f > 200 kHz		3.2		nV/√Hz	C
	Noninverting input current noise	f > 200 kHz		2.8		pA/√Hz	C
	Inverting input current noise	f > 200 kHz		30		pA/√Hz	C
	Closed-loop ac output impedance	f = 20 MHz		0.40		Ω	C
DC PERFORMANCE ⁽⁴⁾
	Open-loop transimpedance gain⁽¹⁾	V_OUT = ±1 V, R_LOAD= 500-Ω	600	1200		kΩ	A
	Closed-loop gain	0.1% external R_F and R_G resistors	2.495	2.515	2.53	V/V	A
INPUT
	External input offset voltage (pin 9 to pin12)	T_J = 25°C	–12	±2.5	12	mV	A
		T_J = 0°C to 70°C	–20		17	mV	B
		T_J = –40°C to +125°C	–31		24	mV	B
	External input offset voltage drift (pin 9 to pin12)	T_J = –40°C to +125°C	-45	–115	–190	µV/°C	B
	Internal input offset voltage (pin 6 to pin 12)	T_J = 25°C	–12	±2.5	12	mV	A
		T_J = 0°C to 70°C	–23		18	mV	B
		T_J = –40°C to +125°C	–35		27	mV	B
	Internal input offset voltage drift (pin 6 to pin 12)	T_J = –40°C to +125°C	–70	–150	–235	µV/°C	B
	External to internal input offset voltage match	T_J = 25°C		±1.2		mV	C
	External noninverting input bias current (pin 9)⁽⁵⁾	T_J = 25°C	–5	±5	15	µA	A
		T_J = 0°C to 70°C	–5.2		15.4	µA	B
		T_J = –40°C to +125°C	–5.6		15.9	µA	B
	External noninverting input bias current drift (pin 9)	T_J = –40°C to +125°C	–3	3	9	nA/°C	B
	Inverting input bias current – either input selected⁽⁵⁾	T_J = 25°C	–40	±5	40	µA	A
		T_J = 0°C to 70°C	–51		46	µA	B
		T_J = –40°C to +125°C	–65		56	µA	B
	Inverting input bias current drift	T_J = –40°C to +125°C	–250	–120	–10	nA/°C	B
	Input headroom to either supply	T_J = 25°C		2.6	3.0	V	A
	Common-mode rejection ratio (CMRR)		47	49		dB	A
	Noninverting input resistance		17.6	18.5	22.4	kΩ	A
	Noninverting input capacitance			3.3		pF	C
	Open-loop inverting input impedance			42		Ω	C
OUTPUT⁽⁶⁾
	Output voltage headroom to either supply	R_LOAD = 500 Ω	1.1	1.3	1.4	V	A
	Linear output current	T_J = 25°C, ±2.5 V into 26-Ω R_LOAD	95	120		mA	A
	Peak output current	0-V output, R_LOAD < 0.2 Ω	135	170		mA	A
	DC output impedance	0-V output, load current = ±40 mA		0.05	0.10	Ω	A
	Internal R_F		17.6	18.5	22.4	kΩ	A
PATHSEL (Pin 4; Logic Reference = Pin 7 = GND)
	Input low logic level	Internal path selected	0.7	0.9		V	A
	Input high logic level	External input selected at VIN (pin 9)		0.9	1.3	V	A
	Input voltage range		–0.5		+V_CC	V	A
	PATHSEL voltage when floated	Internal input from D2S selected	0	20	40	mV	A
	Input pin bias current⁽⁷⁾	0-V input	0		4	µA	A
	Input pin bias current⁽⁷⁾	3.3-V input	–150		–250	µA	A
	Input pin impedance			18 \|\| 1.5		kΩ \|\| pF	C
	Switching time	To 1% of final value		80		ns	C
	Input switching glitch	Both inputs at GND		50		mV	C
	Deselected input dc isolation	± 2-V input	70	80		dB	A
	Deselected input ac isolation	2 V_PP, at 20-MHz input	55	65		dB	C
DISABLE (Pin 10; Logic Reference = Pin 7 = GND)
	Input low logic level		0.7	0.9		V	A
	Input high logic level			0.9	1.3	V	A
	Shutdown control voltage range		–0.5		+V_CC	V	B
	Shutdown voltage when floated	Output stage enabled	0	20	40	mV	A
	Input pin bias current⁽⁷⁾	0-V input	0		4	µA	A
	Input pin bias current⁽⁷⁾	3.3-V input	–150		–250	µA	A
	Input pin impedance			18 \|\| 1.5		kΩ \|\| pF	C
	Switching time (turn on or off)	To 10% of final value		200		ns	C
	Shutdown dc isolation (either input)	±2-V input	70	80		dB	A
	Shutdown ac isolation (either input)	2 V_PP at 20-MHz input	55	65		dB	C
POWER SUPPLY
	Bipolar-supply operating range		±4.0	±6.0	±7.9	V	A
	Single-supply operating range		8	12	15.8	V	B
	Supply current (OPS only)	±6-V supplies	18.5	21	24.5	mA	A
	Disabled supply current in OPS	±6-V supplies	2.0	2.4	3.0	mA	C
	Logic reference current at pin 7⁽⁷⁾	Pins 4, 7, and 10 held at 0 V	200	280	380	µA	A

(1) Output power stage includes an internal 18.5-kΩ feedback resistor. This internal resistor, in parallel with an external 249-Ω R_F and 162-Ω R_G, results in a gain of 2.5 V/V after including a nominal gain loss of 0.9935 V/V due to the input buffer and loop-gain effects.

(2) Test levels (all values set by characterization and simulation): (A) 100% tested at T_A≈ T_J≈ 25°C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information. DC limits tested with no self-heating. Add internal self heating to T_A for T_J.

(3) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (Vpeak / √2) × 2π × f_–3dB.

(4) Output measured at pin 11.

(5) Currents out of pin treated as a positive polarity.

(6) Output measured at pin 11.

(7) Currents out of pin treated as a positive polarity.

7.7 Electrical Characteristics: D2S + OPS

at +V_CC = 6.0 V, –V_CC = –6.0 V, 25-Ω D2S source impedance, D2S input V_IC = 0.25 V, Internal path selected to OPS (PATHSEL ≤ 0.7 V or floated), V_REF = GND, combined A_V = 5 V/V, D2S R_LOAD= 200 Ω, R_F = 249 Ω⁽¹⁾, R_G = 162 Ω (OPS A_V = 2.5 V/V), OPS enabled (DISABLE ≤ 0.7 V or floated), OPS R_LOAD = 100 Ω, and T_J ≈ 25˚C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT	TEST LEVEL ⁽²⁾
AC PERFORMANCE⁽⁴⁾
	Small-signal bandwidth (SSBW)	V_OUT = 100 mV_PP, peaking < 1.5 dB		800		MHz	C
	Large-signal bandwidth (LSBW)	V_OUT = 5 V_PP		500		MHz	C
	Bandwidth for 0.2-dB flatness	V_OUT = 2 V_PP		100		MHz	C
	Slew rate⁽³⁾	V_OUT = 8-V step		5000		V/µs	C
	Over- and undershoot	Input t_r = 1 ns, V_OUT = 5-V step		8%			C
	Rise and fall time	Input t_r = 1 ns, V_OUT = 5-V step		1.1		ns	C
	Settling time to 0.1%	Input t_r = 1 ns, V_OUT = 5-V step		7		ns	C
	2nd-order harmonic distortion (HD2)	f = 20 MHz, V_OUT= 5 V_PP		–60		dBc	C
	3rd-order harmonic distortion (HD3)	f = 20 MHz, V_OUT= 5 V_PP		–75		dBc	C
	Output voltage noise	f > 200 kHz		45		nV/√Hz	C
DC PERFORMANCE⁽⁴⁾
	Total gain D2S to OPS output⁽¹⁾	0.1% tolerance, dc, ±100-mV output test	4.92	5.02	5.12	V/V	A
POWER SUPPLY (Combined D2S, OPS, and Midscale Reference Buffer)
	Bipolar-supply operating range		±4.0	±6.0	±7.9	V	A
	Single-supply operating range		8	12	15.8	V	B
	Supply current	±6-V supplies	51	54	57	mA	A
	Supply current temperature coefficient			10		µA/°C	C

(1) Output power stage includes an internal 18.5-kΩ feedback resistor. This internal resistor, in parallel with an external 249-Ω R_F and 162-Ω R_G, results in a gain of 2.5 V/V after including a nominal gain loss of 0.9935 V/V due to the input buffer and loop-gain effects.

(2) Test levels (all values set by characterization and simulation): (A) 100% tested at T_A≈ T_J≈ 25°C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.

(3) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (Vpeak / √2) × 2π × f_–3dB.

(4) Output measured at pin 11.

7.8 Electrical Characteristics: Midscale (DC) Reference Buffer

at +V_CC = 6.0 V, –V_CC = –6.0 V, R_LOAD = 150 Ω at pin 15, and T_J ≈ 25˚C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT	TEST LEVEL ⁽¹⁾
AC PERFORMANCE (Output measured at pin 15)
	Small-signal bandwidth (SSBW)	V_OUT = 100 mV_PP		400		MHz	C
	Large-signal bandwidth (LSBW)	V_OUT = 1 V_PP		110		MHz	C
	Slew rate⁽²⁾	V_OUT = 4-V step		250		V/µs	C
	Input voltage noise	f > 200 kHz		4.4		nV/√Hz	C
	Input current noise	f > 200 kHz		2.3		pA/√Hz	C
	AC output impedance	f = 20 MHz		1.0		Ω	C
DC AND I/O PERFORMANCE (R_S = 25 Ω, and output measured at pin 15, unless otherwise noted)
	Buffer gain	V_I = ±1 V, R_LOAD = 200 Ω	.9985	0.999	1.001	V/V	A
	Buffer gain drift	T_J = –40°C to +125°C		–1.5	–2.0	ppm/°C	B
	Output offset from midsupply	Input floating, pin 1 open	–120	30	70	mV	A
	Output offset voltage	T_J = 25°C, input driven to 0 V from 0-Ω source	–1.0	4.0	15	mV	A
	Input offset voltage drift	T_J = –40°C to +125°C, input driven to 0 V	–4	3	10	µV/°C	B
	Input bias current⁽³⁾	T_J = 25°C	–15	±1	15	µA	A
	Input bias current drift	T_J = –40°C to +125°C	–8	–2	3	nA/°C	B
	Input/output headroom to either supply	T_J = 25°C, gain change < 1%		1.1	1.4	V	A
	Input impedance	Internal 50-kΩ divider resistors to each supply		22 \|\| 1.5		kΩ \|\| pF	C
	Linear output current into resistive load	±2.25 V into 36 Ω	40	65		mA	A
	DC output impedance	Load current = ±30 mA		0.21		Ω	C

(1) Test levels (all values set by characterization and simulation): (A) 100% tested at T_A≈ T_J≈ 25°C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.

(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (V_PEAK / √2) × 2π × f_–3dB.

(3) Currents out of pin treated as a positive polarity.

7.9 Typical Characteristics: D2S + OPS

at +V_CC = 6 V, –V_CC = –6 V, 25-Ω D2S source impedance , V_IC = 0.25 V, Internal path selected (PATHSEL = GND), V_REF = GND, D2S R_LOAD = 200 Ω at pin 6, R_F = 249 Ω, R_G = 162 Ω, OPS A_V = 2.5 V/V, OPS On (DISABLE = GND), and OPS R_LOAD = 100 Ω at pin 11 (unless otherwise noted)

Figure 1. Frequency Response vs Output Voltage

Figure 3. HD2 vs Frequency

26 units shown

Figure 5. Gain vs Temperature

V_OUT = 500 mV_PP, see Table 2

Figure 7. Small-Signal Frequency Response vs Gain

V_OUT = 5 V_PP

Figure 9. HD2 vs Gain

Test frequency = 20 MHz

Figure 11. HD2 vs Supply Voltage

Figure 2. Small and Large Signal Step Response

Figure 4. HD3 vs Frequency

25-Ω source impedance on each D2S input

Figure 6. Input Referred Differential Noise

V_OUT = 5 V_PP, see Table 2

Figure 8. Large-Signal Frequency Response vs Gain

V_OUT = 5 V_PP

Figure 10. HD3 vs Gain

Test frequency = 20 MHz

Figure 12. HD3 vs Supply Voltage

7.10 Typical Characteristics: D2S Only

at +V_CC = 6.0 V, –V_CC = –6.0 V, fixed gain of 2 V/V, 25-Ω D2S source impedance, V_IC = 0.25 V, external path selected (PATHSEL = +V_CC), V_REF = GND, and D2S R_LOAD = 100 Ω at pin 6 (unless otherwise noted)

V_OUT = 250 mV_PP

Figure 13. Frequency Response vs Input Common-Mode Voltage

R_LOAD = 200 Ω

Figure 15. HD2 vs Output Voltage

Figure 17. Common-Mode Rejection Ratio vs Input Common-Mode Voltage

30 units shown

Figure 19. Output DC Offset Voltage vs Die Temperature

±1-V output pulse

Figure 21. Large-Signal Step Response vs Load Resistance

25-Ω D2S source impedance on each input

Figure 23. VREF Input Pin Frequency Response

V_OUT = 2 V_PP

Figure 14. Frequency Response vs Load Resistance

R_LOAD = 200 Ω

Figure 16. HD3 vs Output Voltage

Figure 18. Differential Input Noise vs Source Impedance

Figure 20. Output Impedance vs Supply Voltage

±1-V output pulse

Figure 22. Large-Signal Pulse Settling Response vs Load Resistance

Figure 24. Simulated Power-Supply Rejection Ratio vs Input Common-Mode Voltage

7.11 Typical Characteristics: OPS only

at +V_CC = 6.0 V, –V_CC = –6.0 V, 25-Ω D2S source impedance, V_REF = GND, R_F = 249 Ω, R_G = 162 Ω, OPS A_V = 2.5V/V, OPS R_LOAD = 100 Ω at pin 11, OPS enabled (DISABLE = GND), and external input path selected (PATHSEL = +V_CC) (unless otherwise noted)

V_OUT = 100 mV_PP, see Table 2 for R_F values vs gain

Figure 25. Frequency Response vs Noninverting Gain

Figure 27. Noninverting Response vs Output Voltage

Figure 29. Noninverting Step Response

Figure 31. HD2 vs Output Voltage

V_OUT = 5 V_PP

Figure 33. HD2 vs Load Resistance

V_OUT = 5 V_PP

Figure 35. HD2 vs Supply Voltage

±100-kHz tone separation, output voltage for each tone

Figure 37. IMD2 vs Output Voltage

Figure 39. Input-Referred Spot Noise vs Frequency

30 units shown

Figure 41. Quiescent Supply Current vs Temperature

See Table 7 for R_F values vs OPS gain

Figure 43. Series Output Resistance vs Load Capacitance

R_F = 205 Ω, A_V = 5 V/V, V_OUT = 10 V_PP, see Figure 43 for R_S value

Figure 45. HD2 vs Load Capacitance

C_LOAD = 200 pF, R_F = 205 Ω, A_V = 5 V/V, see Figure 43 for R_S value

Figure 47. Pulse Response

V_OUT = 100 mV_PP, see Table 4 for R_F values vs gain

Figure 26. Frequency Response vs Inverting Gain

A_V = –2.5 V/V, see Table 4 for R_F value

Figure 28. Inverting Response vs Output Voltage

A_V = –2.5 V/V, see Table 4 for R_F value

Figure 30. Inverting Step Response

Figure 32. HD3 vs Output Voltage

V_OUT = 5 V_PP

Figure 34. HD3 vs Load Resistance

V_OUT = 5 V_PP

Figure 36. HD3 vs Supply Voltage

±100-kHz tone separation, output voltage for each tone

Figure 38. IMD3 vs Output Voltage

Output swing with better than 0.1% linearity

Figure 40. Linear Output Swing vs Load Resistance

±4.5-V input triangular wave, OPS A_V = 2.5 V/V

Figure 42. Output Overdrive Response

V_OUT = 500 mV_PP, see Figure 43 for R_S value

Figure 44. Frequency Response vs Load Capacitance

R_F = 205 Ω, A_V = 5 V/V, V_OUT = 10 V_PP, see Figure 43 for R_S value

Figure 46. HD3 vs Load Capacitance

C_LOAD = 300 pF, R_F = 205 Ω, A_V = 5 V/V, see Figure 43 for R_S value.

Figure 48. Pulse Response

7.12 Typical Characteristics: Midscale (DC) Reference Buffer

at +V_CC = 6.0 V, –V_CC = –6.0 V, R_LOAD = 150 Ω, and T_A ≈ 25˚C (unless otherwise noted)

Figure 49. Frequency Response vs Output Voltage

Figure 51. Buffer Output Impedance vs Load Current

R_LOAD = 150 Ω in parallel with C_LOAD, see the Midscale Buffer ROUT Versus CLOAD Measurement section for circuit setup

Figure 53. Series Output Resistance vs Capacitive Load

Figure 50. Step Response

Figure 52. Buffer Output Offset vs Load Current (I_LOAD)

V_OUT = 100 mV_PP, R_LOAD = 150 Ω in parallel with C_LOAD, see Midscale Buffer ROUT Versus CLOAD Measurement for circuit setup

Figure 54. Frequency Response vs Capacitive Load

7.13 Typical Characteristics: Switching Performance

at +V_CC = 6 V, –V_CC = –6 V, 25-Ω D2S source impedance , V_IC = 0.25 V, Internal path selected (PATHSEL = GND), V_REF = GND, D2S R_LOAD = 200 Ω at pin 6, R_F = 249 Ω, R_G = 162 Ω, OPS On (DISABLE = GND), and OPS R_LOAD = 100 Ω at pin 11 (unless otherwise noted)

D2S Inputs: IN+ = IN– = GND, OPS input: VIN+ = 1 V

Figure 55. PATHSEL Switching Time

Figure 57. OPS Forward Feedthrough in Disable

D2S inputs: IN+ = IN– = GND, OPS input: VIN+ = 1 V

Figure 59. PATHSEL Switching Threshold vs Power Supply

PATHSEL = high, OPS input: VIN+ = 1 V_PP , 10-MHz sine wave

Figure 56. OPS Enable and Disable Time

Figure 58. OPS Reverse Feedthrough in Disable

PATHSEL = high, OPS input: VIN+ = 1 V

Figure 60. OPS Shutdown Threshold vs Power Supply

7.14 Typical Characteristics: Miscellaneous Performance

at +V_CC = 6 V, –V_CC = –6 V, 50-Ω D2S source impedance , V_IC = 0.25 V, internal path selected (PATHSEL = GND), V_REF = GND, D2S R_LOAD = 100 Ω at pin 6, R_F = 249 Ω, R_G = 162 Ω, OPS on (DISABLE = GND), and OPS R_LOAD = 100 Ω at pin 11 (unless otherwise noted)