SLOS358C September 2011 – April 2020 THS4531
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Packaging and Ordering Information
- 6 Electrical Specifications
- 7 Device Information
- 8 Table of Graphs
- 9 Typical Characteristics: VS = 2.7 V
- 10Typical Characteristics: VS = 5 V
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11Application Information
- 11.1 Typical Characteristics Test Circuits
- 11.2
Application Circuits
- 11.2.1 Differential Input to Differential Output Amplifier
- 11.2.2 Single-Ended Input to Differential Output Amplifier
- 11.2.3 Differential Input to Single-Ended Output Amplifier
- 11.2.4 Input Common-Mode Voltage Range
- 11.2.5 Setting the Output Common-Mode Voltage
- 11.2.6 Single-Supply Operation
- 11.2.7 Low Power Applications and the Effects of Resistor Values on Bandwidth
- 11.2.8 Driving Capacitive Loads
- 11.2.9 Audio Performance
- 11.2.10 Audio On and Off Pop Performance
- 11.3 Audio ADC Driver Performance: THS4531 AND PCM4204 Combined Performance
- 11.4 SAR ADC Performance
- 11.5 EVM and Layout Recommendations
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
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11.1.6 Balance Error
The circuit shown in Figure 72 is used to measure the balance error of the main differential amplifier. A network analyzer is used as the signal source and the measurement device. The output impedance of the network analyzer is 50 Ω and is DC coupled. RIT and RG are chosen to impedance match to 50 Ω and maintain the proper gain. To balance the amplifier, a 49.9 Ω resistor to ground is inserted across RIT on the alternate input. The output is measured using a high impedance differential probe at the summing junction of the two RO resistors, with respect to ground.
Figure 72. Balance Error Test Circuit