米6体育平台手机版

7.1 Absolute Maximum Ratings⁽¹⁾

	MIN	MAX	UNIT
Supply voltage, V_S– to V_S+		5.5	V
Input/output voltage, V_IN±, V_OUT±, and V_OCM pins	(V_S–) – 0.7	(V_S+) + 0.7	V
Differential input voltage, V_ID		1	V
Continuous output current, I_O		50	mA
Continuous input current, I_i		0.75	mA
Continuous power dissipation	See Thermal Information
Maximum junction temperature, T_J		150	°C
Operating junction temperature, T_J	–40	125	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_S+	Single-supply voltage	2.7	5	5.4	V
T_A	Ambient temperature	–40	25	125	°C

7.4 Thermal Information

THERMAL METRIC ⁽¹⁾		THS4532	UNIT
		TSSOP (PW)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	122.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	61.2
R_θJB	Junction-to-board thermal resistance	66.7
ψ_JT	Junction-to-top characterization parameter	14.4
ψ_JB	Junction-to-board characterization parameter	66.2
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics: V_S = 2.7 V

Test conditions at T_A = 25°C, V_S+ = 2.7 V, V_S– = 0 V, V_OCM = +V_S/2, V_OUT = 2 V_PP, R_F = 2 kΩ, R_L = 2 kΩ differential, G = 1 V/V, single-ended input, differential output, and input and output referenced to mid-supply, unless otherwise noted.

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT	TEST LEVEL⁽¹⁾
AC PERFORMANCE
Small-signal bandwidth	V_OUT = 100 mV_PP, G = 1		34		MHz	C
	V_OUT = 100 mV_PP, G = 2		16
	V_OUT = 100 mV_PP, G = 5		6
	V_OUT = 100 mV_PP, G = 10		2.7
Gain-bandwidth product	V_OUT = 100 mV_PP, G = 10		27		MHz
Large-signal bandwidth	V_OUT = 2 V_PP, G = 1		34		MHz
Bandwidth for 0.1-dB flatness	V_OUT = 2 V_PP, G = 1		12		MHz
Slew rate, rise/fall, 25% to 75%	V_OUT = 2-V step		190/320		V/µs
Rise/fall time, 10% to 90%			5.2/6.1		ns
Settling time to 1%, rise/fall			25/20		ns
Settling time to 0.1%, rise/fall			60/60		ns
Settling time to 0.01%, rise/fall			150/110		ns
Overshoot/undershoot, rise/fall			1/1%
2nd-order harmonic distortion	f = 1 kHz, V_OUT = 1 V_RMS		–122		dBc
	f = 10 kHz		–127
	f = 1 MHz		–59
3rd-order harmonic distortion	f = 1 kHz, V_OUT = 1 V_RMS		–130		dBc
	f = 10 kHz		–135
	f = 1 MHz		–70
2nd-order intermodulation distortion	f = 1 MHz, 200-kHz tone spacing, V_OUT envelope = 2 V_PP		–83		dBc
3rd-order intermodulation distortion	f = 1 MHz, 200-kHz tone spacing, V_OUT envelope = 2 V_PP		–81		dBc
Input voltage noise	f = 1 kHz		10		nV/√Hz
Voltage noise 1/f corner frequency			45		Hz
Input current noise	f = 100 kHz		0.25		pA/√Hz
Current noise 1/f corner frequency			6.5		kHz
Overdrive recovery time	Overdrive = 0.5 V		65		ns
Output balance error	V_OUT = 100 mV, f = 1 MHz		–65		dB
Closed-loop output impedance	f = 1 MHz (differential)		2.5		Ω
Channel-to-channel crosstalk	f = 10 kHz, measured differentially		-133		dB
DC PERFORMANCE
Open-loop voltage gain (A_OL)		100	113		dB	A
Input-referred offset voltage	T_A = 25°C		±80	±400	µV	A
	T_A = 0°C to 70°C			±715		B
	T_A = –40°C to 85°C			±855
	T_A = –40°C to 125°C			±1300
Input offset voltage drift⁽²⁾	T_A = 0°C to 70°C		±2	±7	µV/°C	B
	T_A = –40°C to 85°C		±2	±7
	T_A = –40°C to 125°C		±3	±9
Input bias current	T_A = 25°C		200	250	nA	A
	T_A = 0°C to 70°C			275		B
	T_A = –40°C to 85°C			286
	T_A = –40°C to 125°C			305
Input bias current drift⁽²⁾	T_A = 0°C to 70°C		0.45	0.55	nA/°C	B
	T_A = –40°C to 85°C		0.45	0.55
	T_A = –40°C to 125°C		0.45	0.55
Input offset current	T_A = 25°C		±5	±50	nA	A
	T_A = 0°C to 70°C			±55		B
	T_A = –40°C to 85°C			±57
	T_A = –40°C to 125°C			±60
Input offset current drift⁽²⁾	T_A = 0°C to 70°C		±0.03	±0.1	nA/°C	B
	T_A= –40°C to 85°C		±0.03	±0.1
	T_A = –40°C to 125°C		±0.03	±0.1
INPUT
Common-mode input low	T_A = 25°C, CMRR > 87 dB		V_S– – 0.2	V_S–	V	A
Common-mode input low	T_A = –40°C to 125°C, CMRR > 87 dB		V_S– – 0.2	V_S–	V	B
Common-mode input high	T_A = 25°C, CMRR > 87 dB	V_S+ – 1.2	V_S+ – 1.1		V	A
Common-mode input high	T_A = –40°C to 125°C, CMRR > 87 dB	V_S+ – 1.2	V_S+ – 1.1		V	B
Common-mode rejection ratio		90	116		dB	A
Input impedance common-mode			200 \|\| 1.2		kΩ \|\| pF	C
Input impedance differential mode			200 \|\| 1		kΩ \|\| pF	C
OUTPUT
Single-ended output voltage: low	T_A = 25°C		V_S– + 0.06	V_S– + 0.2	V	A
Single-ended output voltage: low	T_A = –40°C to 125°C		V_S– + 0.06	V_S– + 0.2	V	B
Single-ended output voltage: high	T_A = 25°C	V_S+ – 0.2	V_S+ – 0.11		V	A
Single-ended output voltage: high	T_A = –40°C to 125°C	V_S+ – 0.2	V_S+ – 0.11		V	B
Output saturation voltage: high/low			110/60		mV	C
Linear output current drive	T_A = 25°C	±15	±22		mA	A
Linear output current drive	T_A = –40°C to 125°C	±15			mA	B
POWER SUPPLY
Specified operating voltage		2.5		5.5	V	B
Quiescent operating current/ch	T_A = 25°C, PD = V_S+		230	330	µA	A
Quiescent operating current/ch	T_A = –40°C to 125°C, PD = V_S+		270	370	µA	B
Power-supply rejection (PSRR)		87	108		dB	A
POWER DOWN
Enable voltage threshold	Specified on above 2.1 V			2.1	V	A
Disable voltage threshold	Specified off below 0.7 V	0.7			V	A
Disable pin bias current	PD = V_S– + 0.5 V		50	500	nA	A
Power-down quiescent current	PD = V_S– + 0.5 V		0.5	2	µA	A
Turn-on time delay	Time from PD = high to V_OUT = 90% of final value, R_L= 200 Ω		650		ns	C
Turn-off time delay	Time from PD = low to V_OUT = 10% of original value, R_L= 200 Ω		20		ns	C
OUTPUT COMMON-MODE VOLTAGE CONTROL (V_OCM)
Small-signal bandwidth	V_OCM input = 100 mV_PP		23		MHz	C
Slew rate	V_OCM input = 1 V_STEP		14		V/µs	C
Gain		0.99	0.996	1.01	V/V	A
Common-mode offset voltage	Offset = output common-mode voltage – V_OCMinput voltage		±1	±5	mV	A
V_OCM input bias current	V_OCM= (V_S+ – V_S–)/2		±20	±100	nA	A
V_OCM input voltage range		0.8	0.75 to 1.9	1.75	V	A
V_OCM input impedance			100 \|\| 1.6		kΩ \|\| pF	C
Default voltage offset from (V_S+ – V_S–)/2	Offset = output common-mode voltage – (V_S+ – V_S–)/2		±3	±10	mV	A

(1) Test levels (all values set by characterization and simulation): (A) 100% tested at +25°C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.

(2) Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end points, computing the difference, and dividing by the temperature range.

Node set to midsupply externally; 0.1 µF

7.6 Electrical Characteristics: V_S = 5 V

Test conditions at T_A = +25°C, V_S+ = 5 V, V_S– = 0 V, V_OCM = open, V_OUT = 2 V_PP, R_F = 2 kΩ, R_L = 2 kΩ differential, G = 1 V/V, single-ended input, differential output, and input and output referenced to mid-supply, unless otherwise noted.

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT	TEST LEVEL⁽¹⁾
AC PERFORMANCE
Small-signal bandwidth	V_OUT = 100 mV_PP, G = 1		36		MHz	C
	V_OUT = 100 mV_PP, G = 2		17
	V_OUT = 100 mV_PP, G = 5		6
	V_OUT = 100 mV_PP, G = 10		2.7
Gain-bandwidth product	V_OUT = 100 mV_PP, G = 10		27		MHz
Large-signal bandwidth	V_OUT = 2 V_PP, G = 1		36		MHz
Bandwidth for 0.1-dB flatness	V_OUT = 2 V_PP, G = 1		15		MHz
Slew rate, rise/fall, 25% to 75%	V_OUT = 2 V_Step		220/390		V/µs
Rise/fall time, 10% to 90%			4.6/5.6		ns
Settling time to 1%, rise/fall			25/20		ns
Settling time to 0.1%, rise/fall			60/60		ns
Settling time to 0.01%, rise/fall			150/110		ns
Overshoot/undershoot, rise/fall			1/1%
2nd-order harmonic distortion	f = 1 kHz, V_OUT = 1 V_RMS		–122		dBc
	f = 10 kHz		–128
	f = 1 MHz		–60
3rd-order harmonic distortion	f = 1 kHz, V_OUT = 1 V_RMS		–130		dBc
	f = 10 kHz		–137
	f = 1 MHz		–71
2nd-order intermodulation distortion	f = 1 MHz, 200-kHz tone spacing, V_OUT envelope = 2 V_PP		–85		dBc
3rd-order intermodulation distortion	f = 1 MHz, 200-kHz tone spacing, V_OUT envelope = 2 V_PP		–83		dBc
Input voltage noise	f = 1 kHz		10		nV/√Hz
Voltage noise 1/f corner frequency			45		Hz
Input current noise	f = 100 kHz		0.25		pA/√Hz
Current noise 1/f corner frequency			6.5		kHz
Overdrive recovery time	Overdrive = 0.5 V		65		ns
Output balance error	V_OUT = 100 mV, f = 1 MHz		–67		dB
Closed-loop output impedance	f = 1 MHz (differential)		2.5		Ω
Channel-to-channel crosstalk	f = 10 kHz, measured differentially		-133		dB
DC PERFORMANCE
Open-loop voltage gain (A_OL)		100	114		dB	A
Input-referred offset voltage	T_A = 25°C		±80	±400	µV	A
	T_A = 0°C to 70°C			±715		B
	T_A = –40°C to 85°C			±855
	T_A = –40°C to 125°C			±1300
Input offset voltage drift⁽²⁾	T_A = 0°C to 70°C		±2	±7	µV/°C	B
	T_A = –40°C to 85°C		±2	±7
	T_A = –40°C to 125°C		±3	±9
Input bias current	T_A = 25°C		200	250	nA	A
	T_A = 0°C to 70°C			279		B
	T_A = –40°C to 85°C			292
	T_A = –40°C to 125°C			315
Input bias current drift⁽²⁾	T_A = 0°C to 70°C		0.5	0.65	nA/°C	B
	T_A = –40°C to 85°C		0.5	0.65
	T_A = –40°C to 125°C		0.5	0.65
Input offset current	T_A = 25°C		±5	±50	nA	A
	T_A = 0°C to 70°C			±55		B
	T_A = –40°C to 85°C			±57
	T_A = –40°C to 125°C			±60
Input offset current drift⁽²⁾	T_A = 0°C to 70°C		±0.03	±0.1	nA/°C	B
	T_A= –40°C to 85°C		±0.03	±0.1
	T_A = –40°C to 125°C		±0.03	±0.1
INPUT
Common-mode input: low	T_A = 25°C, CMRR > 87 dB		V_S– – 0.2	V_S–	V	A
Common-mode input: low	T_A = –40°C to 125°C, CMRR > 87 dB		V_S– – 0.2	V_S–	V	B
Common-mode input: high	T_A = 25°C, CMRR > 87 dB	V_S+ – 1.2	V_S+ –1.1		V	A
Common-mode input: high	T_A = –40°C to 125°C, CMRR > 87 dB	V_S+ – 1.2	V_S+ –1.1		V	B
Common-mode rejection ratio		90	116		dB	A
Input impedance common-mode			200 \|\| 1.2		kΩ \|\| pF	C
Input impedance differential mode			200 \|\| 1		kΩ \|\| pF	C
OUTPUT
Linear output voltage: low	T_A = 25°C		V_S– + 0.1	V_S– + 0.2	V	A
Linear output voltage: low	T_A = –40°C to 125°C		V_S– + 0.1	V_S– + 0.2	V	B
Linear output voltage: high	T_A = 25°C	V_S+ – 0.25	V_S+ – 0.12		V	A
Linear output voltage: high	T_A = –40°C to 125°C	V_S+ – 0.25	V_S+ – 0.12		V	B
Output saturation voltage: high/low			120/100		mV	C
Linear output current drive	T_A = 25°C	±15	±25		mA	A
Linear output current drive	T_A = –40°C to 125°C	±15			mA	B
POWER SUPPLY
Specified operating voltage		2.5		5.5	V	B
Quiescent operating current/ch	T_A = 25°C, PD = V_S+		250	350	µA	A
Quiescent operating current/ch	T_A = –40°C to 125°C, PD = V_S+		290	390	µA	B
Power-supply rejection (PSRR)		87	108		dB	A
POWER DOWN
Enable voltage threshold	Specified on above 2.1 V			2.1	V	A
Disable voltage threshold	Specified off below 0.7 V	0.7			V	A
Disable pin bias current	PD = V_S– + 0.5 V		50	500	nA	A
Power-down quiescent current	PD = V_S– + 0.5 V		0.5	2	µA	A
Turn-on time delay	Time from PD = high to V_OUT = 90% of final value, R_L= 200 Ω		600		ns	C
Turn-off time delay	Time from PD = low to V_OUT = 10% of original value, R_L= 200 Ω		15		ns	C
OUTPUT COMMON-MODE VOLTAGE CONTROL (V_OCM)
Small-signal bandwidth	V_OCM input = 100 mV_PP		24		MHz	C
Slew rate	V_OCM input = 1 V_STEP		15		V/µs	C
Gain		0.99	0.996	1.01	V/V	A
Common-mode offset voltage	Offset = output common-mode voltage – V_OCMinput voltage		±1	±5	mV	A
V_OCMinput bias current	V_OCM= (V_S+ – V_S–)/2		±20	±120	nA	A
V_OCM input voltage range		0.95	0.75 to 4.15	4.0	V	A
V_OCM input impedance			65 \|\| 0.86		kΩ \|\| pF	C
Default voltage offset from (V_S+ – V_S–)/2	Offset = output common-mode voltage – (V_S+ – V_S–)/2		±3	±10	mV	A

(1) Test levels (all values set by characterization and simulation): (A) 100% tested at +25°C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.

(2) Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end points, computing the difference, and dividing by the temperature range.

7.7 Typical Characteristics

Table 3. Table of Graphs

DESCRIPTION	V_S = 2.7 V	V_S = 5 V
Small-signal frequency response	Figure 1	Figure 35
Large-signal frequency response	Figure 2	Figure 36
Large- and small- signal pulse response	Figure 3	Figure 37
Single-ended slew rate vs V_OUTstep	Figure 4	Figure 38
Differential slew rate vs V_OUTstep	Figure 5	Figure 39
Overdrive recovery	Figure 6	Figure 40
10-kHz FFT on audio analyzer	Figure 7	Figure 41
Harmonic distortion vs Frequency	Figure 8	Figure 42
Harmonic distortion vs Output voltage at 1 MHz	Figure 9	Figure 43
Harmonic distortion vs Gain at 1 MHz	Figure 10	Figure 44
Harmonic distortion vs Load at 1 MHz	Figure 11	Figure 45
Harmonic distortion vs V_OCM at 1 MHz	Figure 12	Figure 46
Two-tone, 2nd and 3rd order intermodulation distortion vs Frequency	Figure 13	Figure 47
Single-ended output voltage swing vs Load resistance	Figure 14	Figure 48
Single-ended output saturation voltage vs Load current	Figure 15	Figure 49
Main amplifier differential output impedance vs Frequency	Figure 16	Figure 50
Frequency response vs C_LOAD	Figure 17	Figure 51
R_O vs C_LOAD	Figure 18	Figure 52
Rejection ratio vs Frequency	Figure 19	Figure 53
Crosstalk vs Frequency	Figure 20	Figure 54
Turn-on time	Figure 21	Figure 55
Turn-off time	Figure 22	Figure 56
Input-referred voltage noise and current noise spectral density	Figure 23	Figure 57
Main amplifier differential open-loop gain and phase vs Frequency	Figure 24	Figure 58
Output balance error vs Frequency	Figure 25	Figure 59
V_OCM small signal frequency response	Figure 26	Figure 60
V_OCM large and small signal pulse response	Figure 27	Figure 61
V_OCM input impedance vs frequency	Figure 28	Figure 62
Count vs input offset current	Figure 29	Figure 63
Count vs input offset current temperature drift	Figure 30	Figure 64
Input offset current vs temperature	Figure 31	Figure 65
Count vs input offset voltage	Figure 32	Figure 66
Count vs input offset voltage temperature drift	Figure 33	Figure 67
Input offset voltage vs temperature	Figure 34	Figure 68

7.7.1 Typical Characteristics: V_S = 2.7 V

V_S+ = 2.7 V, V_S– = 0 V, CM = open, V_OUT = 2 Vpp, R_F = 2 kΩ, R_L = 2 kΩ Differential, G = 1V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply unless otherwise noted.

THS4532 G001_Small-Signal_Frequency_Response.gif

V_S = 2.7 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ	V_OUT = 100 mV_PP

Figure 1. Small-Signal Frequency Response

THS4532 G003_Large-_and_Small-Signal_Pulse_Response.gif

V_S = 2.7 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ

Figure 3. Large- and Small-Signal Pulse Response

THS4532 G053_Diff_Slew_Rate_vs_Vout_Step_RL=200.gif

V_S = 2.7 V	G = 2 V/V	R_F = 2 kΩ
R_L = 200 Ω

Figure 5. Differential Slew Rate vs V_OUT Step

THS4532 G006_10_kHz_Output_Spectrum_on_AP_Analyzer_AP_Load_=_100k.gif

V_S = 2.7 V	G = 1 V/V	R_F = 2 kΩ
R_L = 100 Ω	V_OUT = 4 V_PP

Figure 7. 10-kHz FFT On Audio Analyzer

THS4532 G008_Harmonic_Distortion_vs_Output_Voltage_at_1MHz_RF=2k_RL=2k.gif

V_S = 2.7 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ	f = 1 MHz

Figure 9. Harmonic Distortion vs Output Voltage at 1 MHz

THS4532 G010_Harmonic_Distortion_vs_Load_at_1MHz_RF=2k.gif

V_S = 2.7 V	G = 1 V/V	R_F = 2 kΩ
V_OUT = 2 V_PP	f = 1 MHz

Figure 11. Harmonic Distortion vs Load at 1 MHz

THS4532 G012_Two-Tone_Second-_and_Third-Order_Intermodulation_Distortion_vs_Frequency_RF=2k_RL=2k.gif

V_S = 2.7 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ	V_OUT = 2 V_PP	Envelope

Figure 13. Two-Tone, 2^nd and 3^rd Order Intermodulation
Distortion vs Frequency

THS4532 G014_Single-Ended_Output_Saturation_Voltage_vs_Load_Current.gif

V_S = 2.7 V	G = 2 V/V	R_F = 2 kΩ

Figure 15. Single-Ended Output Saturation Voltage vs Load Current

THS4532 G016_Frequency_Response_vs_CLOAD_RLOAD_=_2k.gif

V_S = 2.7 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ	V_OUT = 100 mV_PP

Figure 17. Frequency Response vs C_LOAD

THS4532 G018_Rejection_Ratio_vs_Frequency.gif

V_S = 2.7 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ

Figure 19. Rejection Ratio vs Frequency

THS4532 G019_Turn_on_Time_RF=2k_RL=200.gif

V_S = 2.7 V	G = 1 V/V	R_F = 2 kΩ
R_L = 200 Ω	V_IN = 1 V

Figure 21. Turn-On Time

THS4532 G021_Input-Referred_Voltage_Noise_and_Current_Noise_Spectral_Density.gif

Figure 23. Input-Referred Voltage Noise and Current Noise Spectral Density

THS4532 G023_Output_Balance_Error_vs_Frequency_RF=2k_RL=1k.gif

V_S = 2.7 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ	V

Figure 25. Output Balance Error vs Frequency

THS4532 G025_Vocm_Large-_and_Small_Signal_Pulse_Response_RF=2k.png

Figure 27. V_OCM Large- and Small Signal Pulse Response

V_S = 2.7 V	T_A = 25°C

Figure 29. THS4532IPW Input Offset Current Histogram

THS4532 Figure 31 IOS Over Temp 2_7V.gif

V_S = 2.7 V	Channel 1

Figure 31. THS4532IPW Input Offset Current vs Temperature

V_S = 2.7 V

Both Channels

Figure 33. THS4532IPW Input Offset Voltage Temp Drift Histogram

THS4532 G002_Large-Signal_Frequency_Response.gif

V_S = 2.7 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ	V_OUT = 20 V_PP

Figure 2. Large-Signal Frequency Response

THS4532 G004_Slew_Rate_vs_Vout_Step_RL=200.gif

V_S = 2.7 V	G = 2 V/V	R_F = 2 kΩ
R_L = 200 Ω

Figure 4. Single-Ended Slew Rate vs V_OUT Step

V_S = 2.7 V	G = 2 V/V	R_F = 2 kΩ
R_L = 2 kΩ

Figure 6. Overdrive Recovery

THS4532 G007_Harmonic_Distortion_vs_Frequency_RF=2k_RL=2k.gif

V_S = 2.7 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ	V_OUT =2 V_PP

Figure 8. Harmonic Distortion vs Frequency

THS4532 G009_Harmonic_Distortion_vs_Gain_at_1MHz_RF=2k_RL=2k.gif

V_S = 2.7 V	R_F = 2 kΩ	R_L = 2 kΩ
V_OUT = 2 V_PP	f = 1 MHz

Figure 10. Harmonic Distortion vs Gain at 1 MHz

THS4532 G011_Harmonic_Distortion_vs_Vocm_at_1MHz_RF=2k_RL=2k.gif

V_S = 2.7 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ	V_OUT = 2 V_PP	f = 1 MHz

Figure 12. Harmonic Distortion V_OCM at 1 MHz

THS4532 G013_Single-Ended_Output_Voltage_Swing_vs_Load_Resistance.gif

V_S = 2.7 V	G = 2 V/V	R_F = 2 kΩ

Figure 14. Single-Ended Output Voltage Swing vs Load Resistance

THS4532 G015_Main_Amplifier_Differential_Output_Impedance_vs_Frequency.gif

V_S = 2.7 V	G = 1 V/V	R_F = 2 kΩ
V_OUT = 100 mV_PP

Figure 16. Main Amplifier Differential Output Impedance vs Frequency

V_S = 2.7 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ

Figure 18. R_O vs C_LOAD

V_S = 2.7 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ	V_OUT = 2 V_PP

Figure 20. Crosstalk vs Frequency

THS4532 G020_Turn_Off_Time_RF=2k_RL=200.gif

V_S = 2.7 V	G = 1 V/V	R_F = 2 kΩ
R_L = 200 Ω

Figure 22. Turn-Off Time

THS4532 G022_Main_Amplifier_Differential_Open-Loop_Gain_and_Phase.gif

Figure 24. Main Amplifier Differential Open-Loop Gain and Phase vs Frequency

THS4532 G024_Vocm_Small-Signal_Frequency_Response_RF=2k.gif

V_S = 2.7 V	G = 1 V/V	R_F = 2 kΩ
V_OUT = 100 mV_PP

Figure 26. V_OCM Small-Signal Frequency Response

THS4532 G026_Vocm_Input_Impedance_vs_Frequency.gif

V_S = 2.7 V

Figure 28. V_OCM Input Impedance vs Frequency

V_S = 2.7 V	Both Channels
V_OUT = 100 mV_PP

Figure 30. THS4532IPW Input Offset Current Temp Drift Histogram

V_S = 2.7 V

T_A = 25°C

Figure 32. THS4532IPW Input Offset Voltage Histogram

THS4532 Figure 34 VOS Over Temp 2_7V.gif

V_S = 2.7 V	Channel 1

Figure 34. THS4532IPW Input Offset Voltage vs Temperature

spacer

7.7.2 Typical Characteristics: V_S = 5 V

V_S+ = 5 V, V_S– = 0 V, V_OCM = open, V_OUT = 2 Vpp, R_F = 2 kΩ, R_L = 2 kΩ Differential, G = 1V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply, T_A = 25°C unless otherwise noted.

THS4532 G027_Small-Signal_Frequency_Response.gif

V_S = 5 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ	V_OUT = 100 mV_PP

Figure 35. Small-Signal Frequency Response

THS4532 G029_Large-_and_Small-Signal_Pulse_Response.gif

V_S = 5 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ

Figure 37. Large- and Small-Signal Pulse Response

THS4532 G054_Diff_Slew_Rate_vs_Vout_Step_RL=200.gif

V_S = 5 V	G = 2 V/V	R_F = 2 kΩ
R_L = 200 Ω	V_OUT = 100 mV_PP

Figure 39. Differential Slew Rate vs V_OUT Step

THS4532 G032_10_kHz_Output_Spectrum_on_AP_Analyzer_AP_Load_=_100k.gif

V_S = 5 V	G = 1 V/V	R_F = 2 kΩ
R_L = 100 kΩ	V_OUT = 8 V_PP

Figure 41. 10-kHz FFT On Audio Analyzer

THS4532 G034_Harmonic_Distortion_vs_Output_Voltage_at_1MHz_RF=2k_RL=2k.gif

V_S = 5 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ	f = 1 MHz

Figure 43. Harmonic Distortion vs Output Voltage at 1 MHz

THS4532 G036_Hamonic_Distortion_vs_Load_at_1MHz_RF=2k.gif

V_S = 5 V	G = 1 V/V	R_F = 2 kΩ
V_OUT 2 V_PP	f = 1 MHz

Figure 45. Harmonic Distortion vs Load at 1 MHz

THS4532 G038_Two-Tone_Second-_and_Third-Order_Intermodulation_Distortion_vs_Frequency_RF=2k_RL=2k.gif

V_S = 5 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ	V_OUT = 2 V_PP	Envelope

Figure 47. Two-Tone, 2^nd and 3^rd Order Intermodulation
Distortion vs Frequency

THS4532 G040_Single-Ended_Output_Saturation_Voltage_vs_Load_Current.gif

V_S = 5 V	G = 2 V/V	R_F = 2 kΩ

Figure 49. Single-Ended Output Saturation Voltage vs Load Current

THS4532 G042_Frequency_Response_vs_CLOAD_RLOAD_=_2k.gif

V_S = 5 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ	V_OUT = 100 mV_PP

Figure 51. Frequency Response vs C_LOAD

THS4532 G044_Rejection_Ratio_vs_Frequency.gif

V_S = 5 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ

Figure 53. Rejection Ratio vs Frequency

THS4532 G045_Turn_on_Time_RF=2k_RL=200.gif

V_S = 5 V	G = 1 V/V	R_F = 2 kΩ
R_L = 200 Ω	V_IN = 1 V

Figure 55. Turn-On Time

THS4532 G047_Input-Referred_Voltage_Noise_and_Current_Noise_Spectral_Density.gif

Figure 57. Input-Referred Voltage Noise and Current Noise Spectral Density

THS4532 G049_Output_Balance_Error_vs_Frequency_RF=2k_RL=1k.gif

V_S = 5 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ

Figure 59. Output Balance Error vs Frequency

THS4532 G051_Vocm_Large-_and_Small-Signal_Pulse_Response_RF=2k.gif

Figure 61. V_OCM Large- and Small Signal Pulse Response

V_S = 5 V

T_A = 25°C

Figure 63. THS4532IPW Input Offset Current Histogram

V_S = 5 V	Channel 1

Figure 65. THS4532IPW Input Offset Current vs Temperature

V_S = 5 V

Both Channels

Figure 67. THS4532IPW Input Offset Voltage Temp Drift Histogram

THS4532 G028_Large-Signal_Frequency_Response.gif

V_S = 5 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ	V_OUT = 2 V_PP

Figure 36. Large-Signal Frequency Response

THS4532 G030_Slew_Rate_vs_Vout_Step_RL=200.gif

V_S = 5 V	G = 2 V/V	R_F = 2 kΩ
R_L = 200 Ω

Figure 38. Single-Ended Slew Rate vs V_OUT Step

V_S = 5 V	G = 2 V/V	R_F = 2 kΩ
R_L = 200 Ω	V_OUT = 100 mV_PP

Figure 40. Overdrive Recovery

THS4532 G033_Harmonic_Distortion_vs_Frequency_RF=2k_RL=2k.gif

V_S = 5 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ	V_OUT = 2V_PP

Figure 42. Harmonic Distortion vs Frequency

THS4532 G035_Harmonic_Distortion_vs_Gain_at_1MHz_RF=2k_RL=2k.gif

V_S = 5 V	R_F = 2 kΩ	R_L = 2 kΩ
V_OUT = 2 V_PP	f = 1 MHz

Figure 44. Harmonic Distortion vs Gain at 1 MHz

THS4532 G037_Harmonic_Distortion_vs_Vocm_at_1MHz_RF=2k_RL=2k.gif

V_S = 5 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ	V_OUT = 2 V_PP	f = 1 MHz

Figure 46. Harmonic Distortion vs V_OCM at 1 MHz

THS4532 G039_Single-Ended_Output_Voltage_Swing_vs_Load_Resistance.gif

V_S = 5 V	G = 2 V/V	R_F = 2 kΩ

Figure 48. Single-Ended Output Voltage Swing vs Load Resistance

THS4532 G041_Main_Amplifier_Differential_Output_Impedance_vs_Frequency.gif

V_S = 5 V	G = 1 V/V	R_F = 2 kΩ
V_OUT = 100 mV_PP

Figure 50. Main Amplifier Differential Output Impedance vs Frequency

V_S = 5 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ

Figure 52. R_O vs C_LOAD

V_S = 5 V	G = 1 V/V	R_F = 2 kΩ
R_L = 2 kΩ	V_OUT = 2 V_PP

Figure 54. Crosstalk vs Frequency

THS4532 G046_Turn_off_Time_RF=2k_RL=200.gif

V_S = 5 V	G = 1 V/V	R_F = 2 kΩ
R_L = 200 Ω

Figure 56. Turn-Off Time

THS4532 G048_Main_Amplifier_Differential_Open-Loop_Gain_and_Phase.gif

Figure 58. Main Amplifier Differential Open-Loop Gain and Phase vs Frequency

THS4532 G050_Vocm_Small-Signal_Frequency_Response_RF=2k.gif

V_S = 5 V	G = 1 V/V	R_F = 2 kΩ
V_OUT = 200 mV_PP

Figure 60. V_OCM Small-Signal Frequency Response

THS4532 G052_Vocm_Input_Impedance_vs_Frequency.gif

V_S = 5 V

Figure 62. V_OCM Input Impedance vs Frequency

V_S = 5 V

Both Channels

Figure 64. THS4532IPW Input Offset Current Temp Drift Histogram

V_S = 5 V

T_A = 25°C

Figure 66. THS4532IPW Input Offset Voltage Histogram

V_S = 5 V	Channel 1

Figure 68. THS4532IPW Input Offset Voltage vs Temperature

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7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics: V_S = 2.7 V

7.6 Electrical Characteristics: V_S = 5 V

7.7 Typical Characteristics

Table 3. Table of Graphs

7.7.1 Typical Characteristics: V_S = 2.7 V

7.7.2 Typical Characteristics: V_S = 5 V

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7 Specifications

7.1 Absolute Maximum Ratings(1)

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics: VS = 2.7 V

7.6 Electrical Characteristics: VS = 5 V

7.7 Typical Characteristics

Table 3. Table of Graphs

7.7.1 Typical Characteristics: VS = 2.7 V

7.7.2 Typical Characteristics: VS = 5 V

7.1 Absolute Maximum Ratings⁽¹⁾

7.5 Electrical Characteristics: V_S = 2.7 V

7.6 Electrical Characteristics: V_S = 5 V

7.7.1 Typical Characteristics: V_S = 2.7 V

7.7.2 Typical Characteristics: V_S = 5 V