SLES032E June   2002  – September 2014 THS8200

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Terminal Configuration and Functions
    1. 3.1 Terminal Functions
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  Handling Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Power Consumption Summary
    5. 4.5  Power Supply
    6. 4.6  Digital Inputs, DC Characteristics
    7. 4.7  Analog (DAC) Outputs
    8. 4.8  Nonlinearity
      1. 4.8.1 Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for 700 mV Without Bias
      2. 4.8.2 Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for 700 mV + 350-mV Bias
      3. 4.8.3 Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for 1.25 V Without Bias
    9. 4.9  Analog Output Bandwidth (sinx/x corrected) at fS = 205 MSPS
    10. 4.10 Output Compliance vs Full-Scale Adjustment Resistor Value
    11. 4.11 Vertical Sync of the HDTV 1080I Format Preset in First and Second Field, and Horizontal Line Waveform Detail
  5. 5 Functional Overview
    1. 5.1 Data Manager (DMAN)
      1. 5.1.1  Interpolating Finite Impulse Responses Filter (IFIR)
      2. 5.1.2  Color-Space Conversion (CSC)
      3. 5.1.3  Clip/Shift/Multiplier (CSM)
      4. 5.1.4  Digital Multiplexer (DIGMUX)
      5. 5.1.5  Display Timing Generator (DTG)
      6. 5.1.6  Clock Generator (CGEN)
      7. 5.1.7  Clock Driver (CDRV)
      8. 5.1.8  I2C Host Interface (I2CSLAVE)
      9. 5.1.9  Test Block (TST)
      10. 5.1.10 D/A Converters (DACs)
  6. 6 Detailed Functional Description
    1. 6.1  Data Manager (DMAN)
    2. 6.2  Input Interface Formats
    3. 6.3  Clock Generator (CGEN)/Clock Driver (CDRV)
    4. 6.4  Color Space Conversion (CSC)
    5. 6.5  Clip/Shift/Multiplier (CSM)
      1. 6.5.1 Clipping
      2. 6.5.2 Shifting
      3. 6.5.3 Multiplying
    6. 6.6  Interpolating Finite Impulse Response Filter (IFIR)
    7. 6.7  Display Timing Generator (DTG)
      1. 6.7.1 Overview of Functionality
      2. 6.7.2 Functional Description
        1. 6.7.2.1 Predefined DTG Video Formats (Presets)
        2. 6.7.2.2 Internal Synchronization
        3. 6.7.2.3 Output Synchronization: Composite Sync
        4. 6.7.2.4 Output Synchronization: Hsync/Vsync Outputs
      3. 6.7.3 DTG Line Type Overview
        1. 6.7.3.1  HDTV Mode
        2. 6.7.3.2  Active Video
        3. 6.7.3.3  FULL NTSP (Full Normal Tri-Level Sync Pulse)
        4. 6.7.3.4  NTSP NTSP (Normal Tri-Level Sync Pulse/Normal Tri-Level Sync Pulse)
        5. 6.7.3.5  BTSP BTSP (Broad Pulse and Tri-Level Sync Pulse/Broad Pulse and Tri-Level Sync Pulse)
        6. 6.7.3.6  NTSP BTSP (Normal Tri-Level Sync Pulse/ Broad Pulse and Tri-Level Sync Pulse)
        7. 6.7.3.7  BTSP NTSP (Broad Pulse and Tri-Level Sync Pulse/Normal Tri-Level Sync Pulse)
        8. 6.7.3.8  Full BTSP (Full Broad Pulse and Tri-Level Sync Pulse)
        9. 6.7.3.9  SDTV Mode
        10. 6.7.3.10 NEQ_NEQ (Negative Equalization Pulse/Negative Equalization Pulse)
        11. 6.7.3.11 FULL_BSP (Full Broad Sync Pulse)
        12. 6.7.3.12 BSP_BSP (Broad Sync Pulse/Broad Sync Pulse)
        13. 6.7.3.13 FULL_NSP (Full Normal Sync Pulse)
        14. 6.7.3.14 NEQ_BSP (Negative Equalization Pulse/Broad Sync Pulse)
        15. 6.7.3.15 BSP_NEQ (Broad Sync Pulse/Negative Equalization Pulse)
        16. 6.7.3.16 FULL_NEQ (Full Negative Equalization Pulse)
        17. 6.7.3.17 NSP_ACTIVE (Normal Sync Pulse/Active Video)
        18. 6.7.3.18 ACTIVE_NEQ (Active Video/Negative Equalization Pulse)
        19. 6.7.3.19 ACTIVE VIDEO
    8. 6.8  D/A Conversion
      1. 6.8.1 RGB Output Without Sync Signal Insertion/General-Purpose Application DAC
      2. 6.8.2 SMPTE-Compatible RGB Output With Sync Signal Inserted on G (Green) Channel
      3. 6.8.3 SMPTE-Compatible Analog-Level Output With Sync Inserted on All RGB Channels
      4. 6.8.4 SMPTE-Compatible YPbPr Output With Sync Signal Inserted on Y Channel Only
      5. 6.8.5 SMPTE-Compatible YPbPr Output With Sync Signal Inserted on All Channels
      6. 6.8.6 Summary of Supported Video Formats
    9. 6.9  Test Functions
    10. 6.10 Power Down
    11. 6.11 CGMS Insertion
    12. 6.12 I2C Interface
  7. 7 I2C Registers
    1. 7.1 I2C Register Map
    2. 7.2 Register Descriptions
      1. 7.2.1 System Control (Sub-Addresses 0x02−0x03)
      2. 7.2.2 Color Space Conversion Control (Sub-Addresses 0x04−0x19)
      3. 7.2.3 Test Control (Sub-Addresses 0x1A−0x1B)
      4. 7.2.4 Data Path Control (Sub-Address 0x1C)
      5. 7.2.5 Display Timing Generator Control, Part 1 (Sub-Addresses 0x1D−0x3C)
      6. 7.2.6 DAC Control (Sub-Addresses 0x3D−0x40)
      7. 7.2.7 Clip/Shift/Multiplier Control (Sub-Addresses 0x41−0x4F)
      8. 7.2.8 Display Timing Generator Control, Part 2 (Sub-Addresses 0x50−0x82)
      9. 7.2.9 CGMS Control (Sub-Addresses 0x83−0x85)
    3. 7.3 THS8200 Preset Mode Line Type Definitions
      1. 7.3.1 SMPTE_274P (1080P)
      2. 7.3.2 274M Interlaced (1080I)
      3. 7.3.3 296M Progressive (720P)
      4. 7.3.4 SDTV 525 Interlaced Mode
      5. 7.3.5 SDTV 525 Progressive Mode
      6. 7.3.6 SDTV 625 Interlaced Mode
  8. 8 Application Information
    1. 8.1 Video vs Computer Graphics Application
    2. 8.2 DVI to Analog YPbPr/RGB Application
    3. 8.3 Master vs Slave Timing Modes
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Getting Started and Next Steps
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Community Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

2 Revision History

Changes from D Revision (February 2010) to E Revision

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