ZHCSQ45A january 2023 – july 2023 THVD1454
PRODUCTION DATA
The differential receiver of the THVD1454 is failsafe to invalid bus states caused by the following:
In any of these cases, the differential receiver outputs a failsafe logic high state so that the output of the receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output must output a high when the differential input VID is more positive than 200 mV, and must output a low when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are VTH+, VTH–, and VHYS (the separation between VTH+ and VTH–). As shown in the Table 8-2, differential signals more negative than –200 mV always causes a low receiver output, and differential signals more positive than 200 mV always causes a high receiver output.
When the differential input signal is close to zero, it is still above the VTH+ threshold, and the receiver output is high. Only when the differential input is more than VHYS below VTH+ does the receiver output transition to a low state. Therefore, the noise immunity of the receiver inputs during a bus fault conditions includes the receiver hysteresis value, VHYS, as well as the value of VTH+.