ZHCSPL9A January 2024 – August 2024 THVD2419 , THVD2429
PRODUCTION DATA
The differential receivers of the THVD24x9 family are failsafe to invalid bus states caused by the following:
In any of these cases, the receiver outputs a fail-safe logic high state if the input amplitude stays for longer than tD(OFS) at less than |VTH_FSH|.