ZHCSOO2B December 2022 – March 2024 THVD2410V , THVD2412V , THVD2450V , THVD2452V
PRODUCTION DATA
When the driver enable pin, DE, is logic high (H), the differential outputs A/Y and B/Z follow the logic states at data input D. A logic high at D causes A/Y to turn high and B/Z to turn low. In this case, the differential output voltage defined as VOD = VA – VB is positive. When D is low (L), the output states reverse: B/Z turns high, A/Y becomes low, and VOD is negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant (X). The DE pin has an internal pull-down resistor to ground; thus, when left open the driver is disabled (Z = high-impedance) by default. The D pin has an internal pull-up resistor to VIO; thus, when left open while the driver is enabled, output A/Y turns high and B/Z turns low.
| INPUT | ENABLE | OUTPUTS | FUNCTION | |
|---|---|---|---|---|
| D | DE | A/Y | B/Z | |
| H | H | H | L | Actively drive bus high |
| L | H | L | H | Actively drive bus low |
| X | L | Z | Z | Driver disabled |
| X | OPEN | Z | Z | Driver disabled by default |
| OPEN | H | H | L | Actively drive bus high by default |
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high. When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+ and VTH- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).
| DIFFERENTIAL INPUT | ENABLE | OUTPUT | FUNCTION |
|---|---|---|---|
| VID = VA – VB | RE | R | |
| VTH+ < VID | L | H | Receive valid bus high |
| VTH- < VID < VTH+ | L | ? | Indeterminate bus state |
| VID < VTH- | L | L | Receive valid bus low |
| X | H | Z | Receiver disabled |
| X | OPEN | Z | Receiver disabled by default |
| Open-circuit bus | L | H | Fail-safe high output |
| Short-circuit bus | L | H | Fail-safe high output |
| Idle (terminated) bus | L | H | Fail-safe high output |
Table 7-3 shows SLR (slew rate select) pin functionality. SLR has intergated pull-down, so the device remains in higher speed mode until SLR is pulled high which limits the slew rate and puts the device in slower speed mode.
| Device | Functionality w.r.t SLR pin |
|---|---|
| THVD2410V, THVD2412V | SLR = Low or floating: Both transmitter (TX) and receiver (RX)
maximum speed is 1 Mbps SLR = High: Both TX and RX maximum speed is limited to 250 kbps |
| THVD2450V, THVD2452V | SLR = Low or floating: Both transmitter (TX) and receiver (RX)
maximum speed is 50 Mbps SLR = High: Both TX and RX maximum speed is limited to 20 Mbps |
Table shows the device behavior in undervoltage scenarios:
| VCC | VIO | Driver Output | Receiver Output |
|---|---|---|---|
| > UVVCC(rising) | > UVVIO(rising) | Determined by DE and D inputs | Determined by RE and A-B |
| < UVVCC(falling) | > UVVIO(rising) | High impedance | High impedance |
| > UVVCC(rising) | < UVVIO(falling) | High impedance | High impedance |
| < UVVCC(falling) | < UVVIO(falling) | High impedance | High impedance |