ZHCSOO2B December   2022  – March 2024 THVD2410V , THVD2412V , THVD2450V , THVD2452V

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Ratings [IEC]
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Power Dissipation
    7. 5.7  Electrical Characteristics
    8. 5.8  Switching Characteristics_250 kbps
    9. 5.9  Switching Characteristics_1 Mbps
    10. 5.10 Switching Characteristics_20 Mbps
    11. 5.11 Switching Characteristics_50 Mbps
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 ±70 V Fault Protection
      2. 7.3.2 Integrated IEC ESD and EFT Protection
      3. 7.3.3 Driver Overvoltage and Overcurrent Protection
      4. 7.3.4 Enhanced Receiver Noise Immunity
      5. 7.3.5 Receiver Fail-Safe Operation
      6. 7.3.6 Low-Power Shutdown Mode
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Stub Length
        3. 8.2.1.3 Bus Loading
        4. 8.2.1.4 Transient Protection
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 商标
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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5.7 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted). All typical values are at 25°C and supply voltage of VCC = 5 V, VIO = 3.3 V , unless otherwise noted. (1) 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver
|VOD| Driver differential output voltage magnitude RL = 60 Ω, –25 V ≤ Vtest ≤ 25 V (See Figure 6-1 ) 1.5 3.3 V
RL = 60 Ω, –25 V ≤ Vtest ≤ 25 V, 4.5 V ≤ VCC ≤ 5.5 V (See Figure 6-1 ) 2.1 3.3 V
RL = 100 Ω (See Figure 6-2 ) 2 4 V
RL = 54 Ω (See Figure 6-2 ) 1.5 3.5 V
Δ|VOD| Change in differential output voltage RL = 54 Ω or 100 Ω (See Figure 6-2 ) –50 50 mV
VOC Common-mode output voltage RL = 54 Ω or 100 Ω (See Figure 6-2 ) 1 VCC/2 3 V
ΔVOC(SS) Change in steady-state common-mode output voltage RL = 54 Ω or 100 Ω (See Figure 6-2 ) –50 50 mV
IOS Short-circuit output current DE = VIO, -70 V ≤ (VA or VB) ≤ 70 V, or A shorted to B (A,B are driver terminals for half duplex, Y/Z are for full duplex) –250 250 mA
Receiver
II Bus input current DE = 0 V, VCC and VIO = 0 V or 5.5 V VI = 12 V 90 125 μA
VI = 25 V 200 250 μA
VI = –7 V –100 –80 μA
VI = –25 V –350 –220 μA
VTH+ Positive-going input threshold voltage (2) Over common-mode range of ± 25 V THVD2410V, THVD2450V 40 125 200 mV
VTH- Negative-going input threshold voltage (2) Over common-mode range of ± 25 V THVD2410V, THVD2450V –200 –125 -40 mV
VTH+ Positive-going input threshold voltage (2) Over common-mode range of ± 25 V THVD2412V, THVD2452V 20 125 200 mV
VTH- Negative-going input threshold voltage (2) Over common-mode range of ± 25 V THVD2412V, THVD2452V –200 –125 -20 mV
VHYS Input hysteresis Over common-mode range of ± 25 V 250 mV
VTH_FSH Input fail-safe threshold Over common-mode range of ± 25 V THVD2410V, THVD2450V –40 40 mV
VTH_FSH Input fail-safe threshold Over common-mode range of ± 25 V THVD2412V, THVD2452V –20 20 mV
CA,B Input differential capacitance Measured between A and B, f = 1 MHz 50 pF
VOH Output high voltage IOH = –8 mA, VIO = 3 to 3.6 V or 4.5 V to 5.5 V VIO – 0.4 VIO – 0.2 V
VOL Output low voltage IOL = 8 mA, VIO = 3 to 3.6 V or 4.5 V to 5.5 V 0.2 0.4 V
VOH Output high voltage IOH = –4 mA, VIO = 1.65 to 1.95 V or 2.25 V to 2.75 V VIO – 0.4 VIO – 0.2 V
VOL Output low voltage IOL = 4 mA, VIO = 1.65 to 1.95 V or 2.25 V to 2.75 V 0.2 0.4 V
IOZ Output high-impedance current, R pin VO = 0 V or VIO, RE = VIO –1 1 µA
Logic
IIN Input current (DE , SLR) 1.65 V ≤ VIO ≤ 5.5 V, 0 V ≤ VIN ≤ VIO 5 µA
IIN Input current (D, RE) 1.65 V ≤ VIO ≤ 5.5 V, 0 V ≤ VIN ≤ VIO –5 µA
Thermal Protection
TSHDN Thermal shutdown threshold Temperature rising 150 180 °C
THYS Thermal shutdown hysteresis 10 °C
Supply
UVVCC (rising) Rising under-voltage threshold on VCC 2.3 2.6 V
UVVCC (falling) Falling under-voltage threshold on VCC 1.95 2.2 V
UVVCC(hys) Hysteresis on under-voltage of VCC 170 mV
UVVIO (rising) Rising under-voltage threshold on VIO 1.4 1.6 V
UVVIO (falling) Falling under-voltage threshold on VIO 1.2 1.3 V
UVVIO(hys) Hysteresis on under-voltage of VIO 120 mV
ICC Supply current (quiescent), VCC = 4.5 V to 5.5 V Driver and receiver enabled RE = 0 V, DE = VIO, No load 3.5 5.3 mA
Driver enabled, receiver disabled RE = VIO, DE = VIO, No load 2.5 4.2 mA
Driver disabled, receiver enabled RE = 0 V, DE = 0 V, No load 1.8 2.4 mA
Driver and receiver disabled RE = VIO, DE = 0 V, D = open, No load 0.1 1.2 µA
ICC Supply current (quiescent), VCC = 3 V to 3.6 V Driver and receiver enabled RE = 0 V, DE = VIO, No load 3 4.1 mA
Driver enabled, receiver disabled RE = VIO, DE = VIO, No load 2 3 mA
Driver disabled, receiver enabled RE = 0 V, DE = 0 V, No load 1.6 2.2 mA
Driver and receiver disabled RE = VIO, DE = 0 V, D = open, No load 0.1 1 µA
IIO Logic supply current (quiescent), VIO = 3 to 3.6 V Driver disabled, Receiver enabled, SLR = GND DE = 0 V, RE = 0 V, No load 4.5 8.4 µA
Driver disabled, Receiver enabled, SLR = VIO DE = 0 V, RE = 0 V, No load 3.3 8.4 µA
Driver disabled, Receiver disabled, SLR = GND DE = 0 V, RE = VIO, No load 0.1 1 µA
Driver disabled, Receiver disabled, SLR = VIO DE = 0 V, RE = VIO, No load 1.8 4 µA
(1) A, B are driver output and receiver input terminals for Half duplex devices; A/B are Receiver input, Y/Z are driver output terminals for Full duplex devices
(2) Under any specific conditions, VTH+ is specified to be at least VHYS higher than VTH–.
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