Use the following procedures to calculate thresholds to program to the TIC10024-Q1 for proper switch detection:

1. Calculate the equivalent resistance values at the 2 switch states, taking into account R_DIRT and the 8% resistance variation.
2. Estimate the voltage established when wetting current flows through the switch by utilizing the relationship V_INX = R_{SW_EQU} × I_{WETT_ACT}, where R_{SW_EQU} is the equivalent switch resistance value and I_{WETT_ACT} is the actual wetting current flowing through the switch. The 10 mA wetting current setting is selected in this design as required by the specification. The wetting current variation, however, can occur depending on manufacturing process variation and operating temperature, and needs to be taken into account. Referring to the electrical table of the TIC10024-Q1 and assuming enough headroom for the current source (CSO) to operate, the 10mA wetting current setting produces current ranging between 8.4 mA and 11.4 mA (for 6 V ≤ V_S ≤ 35 V condition). The voltage established on the TIC10024-Q1 input pin (V_INX) can be calculated accordingly.
3. After the V_INX voltage is calculated for the 2 switch states, the proper threshold value needs to be chosen between minimum V_INX voltage of state 1 (>10 V) and maximum V_INX voltage of state 2 (3.32 V). The TIC10024-Q1 has 4 thresholds that can be configured for the comparator: 2 V, 2.7 V, 3 V, and 4 V. As a result, the proper threshold to be used in this design example is 4 V.
4. To properly program the device, follow the below recommend procedure:
   • Enable channel IN0 by setting IN_EN_0 bit to 1 in the IN_EN register
   • Program the wetting current to source by setting CS_IN0 bit to 0 in the CS SELECT register
   • Program the wetting current to 10 mA by configuring WC_IN0_IN1 bits to 100 in the WC_CFG0 register
   • Disable wetting current auto-scaling by setting AUTO_SCALE_DIS_CSO bit in WC_CFG1 register to 1
   • Program the comparator threshold to 4 V by setting the THRES_COMP_IN0_IN3 bits to 11 in the THRES_COMP register
   • Program interrupt generation to both rising and falling transitions by setting the INC_EN_0 bits to 11 in the INT_EN_COMP1 register
   • Enable interrupt generation from switch state change by setting the SSC bit to 1 in the INT_EN_CFG0 register
   • Program the CONFIG register: Keep the device in continuous mode by setting the POLL_EN bit to 0. Start device operation by setting the TRIGGER bit to 1.
   • Read the INT_STAT register to clear the baseline SSC interrupt once the interrupt is observed.
   • Toggle the external switch open and monitor the INT pin. Read the INT_STAT register and IN_STATE_COMP register to make sure the correct switch status is reported.