Interrupt idle time (t_{INT_IDLE}) is implemented in TIC10024-Q1 to:

• Allow the INT pin enough time to be pulled back high by the external pull-up resistor and allow the next assertion to be detectable by an edge-triggered microcontroller.
• Minimize the chance of glitching on the INT pin if back-to-back events occur.

When there is a pending interrupt event and the interrupt event is not masked, t_{INT_IDLE} is applied after the READ command is issued to the INT_STAT register. If another event occurs during the interrupt idle time the INT_STAT register content is updated instantly but the INT pin is not asserted low until t_{INT_IDLE} has elapsed. If another READ command is issued to the INT_STAT register during t_{INT_IDLE}, the INT_STAT register content is cleared immediately, but the INT pin is not re-asserted back low after t_{INT_IDLE} has elapsed. An example of the interrupt idle time is given below to illustrate the INT pin behavior under the static INT assertion schemes: