If V_S voltage rises above V_{OV_R}, the TIC10024-Q1 enters the over-voltage (OV) condition to prevent damage to internal structures of the device on the V_S and INx (for battery-connected switches) pins. The following describes the behavior of the TIC10024-Q1 under OV condition:

1. All current sources and sinks de-activate and switch monitoring stops.
2. Interrupt is generated by asserting the INT pin low and the bit OV in the interrupt register (INT_STAT) is flagged to logic 1. The bit OV_STAT is asserted to logic 1 in the register IN_STAT_MISC. The OI SPI flag is asserted during any SPI transactions. The INT pin is released and the interrupt register (INT_STAT) is cleared on the rising edge of CS provided that the interrupt register has been read during the SPI transaction.
3. SPI communication stays active, and all register settings stay intact without resetting. Previous switch status, if needed, can be retrieved without any interruption.
4. The device continues to monitor the V_S voltage, and the OV condition sustains if the V_S voltage continues to stay above V_{OV_R}- V_{OV_HYST}. No further interrupt is generated once cleared.

When the V_S voltage drops below V_{OV_R} - V_{OV_HYST}, the INT pin is asserted low to notify the microcontroller that the over-voltage condition no longer exists. The OV bit in the register INT_STAT is flagged to logic 1 and the bit OV_STAT bit is de-asserted to logic 0 in the register IN_STAT_MISC to reflect the clearance of the OV condition. The device resumes operation using current register settings (regardless of the INT pin and SPI communication status) with polling restarted from the first enabled channel. The Switch State Change (SSC) interrupt is generated at the end of the first polling cycle and the detected switch status becomes the baseline status for subsequent polling cycles. The content of the INT_STAT register, once read by the microcontroller, is cleared and the INT pin is released afterwards.