TIC12400-Q1 supports two configurable schemes for INT assertion: static and dynamic. The scheme can be adjusted by configuring the INT_CONFIG bit in the CONFIG register.

If the static INT assertion scheme is used (INT_CONFIG = 0 in the CONFIG register), the INT pin is asserted low upon occurrence of an event. The INT pin is released on the rising edge of CS only if a READ command has been issued to read the INT_STAT register while CS is low, otherwise the INT will be kept low indefinitely. The content of the INT_STAT interrupt register is latched on the first rising edge of SCLK after CS goes low for every SPI transaction, and the content is cleared upon a READ command issued to the INT_STAT register, as illustrated in Figure 8-5.

Figure 8-5 Static INT Assertion Scheme

In some system implementations an edge-triggered based microcontroller might potentially miss the INT assertion if it is configured to the static scheme, especially when the microcontroller is in the process of waking up. To prevent missed INT assertion and improve robustness of the interrupt behavior, the TIC12400-Q1 provides the option to use the dynamic assertion scheme for the INT pin. When the dynamic scheme is used (INT_CONFIG= 1 in the CONFIG register), the INT pin is asserted low for a duration of t_{INT_ACTIVE} and is de-asserted back to high if the INT_STAT register has not been read after t_{INT_ACTIVE} has elapsed. The INT is kept high for a duration of t_{INT_INACTIVE}, and is re-asserted low after t_{INT_INACTIVE} has elapsed. The INT pin continues to toggle until the INT_STAT register is read.

If the INT_STAT register is read when INT pin is asserted low, the INT pin is released on the READ command’s CS rising edge and the content of the INT_STAT register is also cleared, as shown in Figure 8-6. If the INT_STAT register is read when INT pin is de-asserted, the content of the INT_STAT register is cleared on the READ command’s CS rising edge, and the INT pin is not re-asserted back low, as shown in Figure 8-7.

Figure 8-6 Dynamic INT Assertion Scheme With INT_STAT Register Read During t_{INT_ACTIVE}

Figure 8-7 Dynamic INT Assertion Scheme With INT_STAT Register Read During t_{INT_INACTIVE}

The static INT assertion scheme is selected by default upon device reset. The INT pin assertion scheme can only be changed when bit TRIGGER is logic 0 in the CONFIG register.