The TIC12400-Q1 uses parity bit check to ensure error-free data transmission from and to the SPI controller.

The device uses odd parity, for which the parity bit is set so that the total number of ones in the transmitted data on SO (including the parity bit) is an odd number (that is Bit0 ⊕ Bit1 ⊕ – ⊕ Bit30 ⊕ Bit31⊕ Parity = 1).

The device also uses odd parity check after receiving data on SI from the SPI controller. If the total number of ones in the received data (including the parity bit) is an even number the received data is discarded. The INT will be asserted low and the PRTY_FAIL bit in the interrupt register (INT_STAT) is flagged to logic 1 to notify the host that transmission error occurred. The PRTY_FAIL flag is also asserted during SPI communications.