ZHCSS29R April   2004  – April 2024 TL103W , TL103WA , TL103WB

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics: OP AMP1 (VREF at Noninverting input)
    6. 5.6 Electrical Characteristics: OP AMP2 (Independent Amplifier)
    7. 5.7 Typical Characteristics: TL103WB
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Internal Reference
      2. 6.3.2 Input Common Mode Range
      3. 6.3.3 EMI Rejection
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Isolated Flyback CC/CV Feedback
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Constant Current Circuit
          2. 7.2.1.2.2 Constant Voltage Circuit
      2. 7.2.2 Constant Current Sink
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 接收文档更新通知
    3. 8.3 支持资源
    4. 8.4 Trademarks
    5. 8.5 静电放电警告
    6. 8.6 术语表
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

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机械数据 (封装 | 引脚)
  • D|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

Input Common Mode Range

The valid common mode range is from device ground to VCC+ – 1.5V (VCC+ – 2V across temperature). Inputs may exceed VCC+ up to the absolute maximum voltage without device damage. At least one input must be in the valid input common-mode range for the output to be the correct phase. If both inputs exceed the valid range, then the output phase is undefined. If either input is more than 0.3V below VCC- then input current should be limited to 1mA and the output phase is undefined.