ZHCSKJ6 December   2019 TL16C750E

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     方框图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. Table 1. Absolute Maximum Ratings
    2. 7.1      ESD Ratings
    3. Table 2. Recommended Operating Conditions
    4. Table 3. Thermal Information
    5. Table 4. Electrical Characteristics
    6. Table 5. Timing Requirements
    7. 7.2      Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1  UART Modes
      2. 9.3.2  Trigger Levels
      3. 9.3.3  Hardware Flow Control
      4. 9.3.4  Auto-RTS
      5. 9.3.5  Auto-CTS
      6. 9.3.6  Software Flow Control
      7. 9.3.7  Software Flow Control Example
      8. 9.3.8  Reset
      9. 9.3.9  Interrupts
      10. 9.3.10 Interrupt Mode Operation
      11. 9.3.11 Polled Mode Operation
      12. 9.3.12 Break and Timeout Conditions
      13. 9.3.13 Programmable Baud Rate Generator with Fractional Divisor
      14. 9.3.14 Fractional Divisor
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Interface Mode
        1. 9.4.1.1 IOR Used (MODE = VCC)
        2. 9.4.1.2 IOR Unused (MODE = GND)
      2. 9.4.2 DMA Signaling
        1. 9.4.2.1 Single DMA Transfers (DMA Mode 0 or FIFO Disable)
        2. 9.4.2.2 Block DMA Transfers (DMA Mode 1)
      3. 9.4.3 Sleep Mode
    5. 9.5 Register Maps
      1. 9.5.1  Registers Operations
      2. 9.5.2  Receiver Holding Register (RHR)
      3. 9.5.3  Transmit Holding Register (THR)
      4. 9.5.4  FIFO Control Register (FCR)
      5. 9.5.5  Line Control Register (LCR)
      6. 9.5.6  Line Status Register (LSR)
      7. 9.5.7  Modem Control Register (MCR)
      8. 9.5.8  Modem Status Register (MSR)
      9. 9.5.9  Interrupt Enable Register (IER)
      10. 9.5.10 Interrupt Identification Register (IIR)
      11. 9.5.11 Enhanced Feature Register (EFR)
      12. 9.5.12 Divisor Latches (DLL, DLH, DLF)
      13. 9.5.13 Transmission Control Register (TCR)
      14. 9.5.14 Trigger Level Register (TLR)
      15. 9.5.15 FIFO Ready Register
      16. 9.5.16 Alternate Function Register (AFR)
      17. 9.5.17 RS-485 Mode
      18. 9.5.18 IrDA Overview
      19. 9.5.19 IrDA Encoder Function
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Set the desired baud rate
        2. 10.2.2.2 Reset the fifos
        3. 10.2.2.3 Sending data on the bus
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Table 5. Timing Requirements

TA = -40°C to 105°C, VCC = 1.8 V to 5 V ±10% (unless otherwise noted)
LIMITS UNIT
1.8 V 2.5 V 3.3 V 5 V
MIN MAX MIN MAX MIN MAX MIN MAX
IOR Used (MODE = VCC)
tRESET Reset pulse width 200 200 200 200 ns
CP CP clock period 63 42 20 20 ns
t3w Oscillator or clock speed 16 24 48 48 MHz
t6s Address setup time 65 45 30 20 ns
t6h Address hold time See Figure 2 and Figure 4 15 10 7 5 ns
t7w IOR strobe width See Figure 2 and Figure 4 85 70 50 40 ns
t9w Read cycle delay See Figure 4 85 70 60 50 ns
t12d Delay from IOR to data See Figure 4 90 55 35 25 ns
t12h Data disable time 45 30 20 15 ns
t13w IOW strobe width See Figure 2 85 70 50 40 ns
t15w Write cycle delay See Figure 2 85 70 60 50 ns
t16s Data setup time See Figure 2 70 50 30 20 ns
t16h Data hold time See Figure 2 35 25 15 10 ns
t17d Delay from IOW to output 50-pF load, see Figure 6 80 50 35 25 ns
t18d Delay to set interrupt from MODEM input 50-pF load, see Figure 6 120 80 50 35 ns
t19d Delay to reset interrupt from IOR 50-pF load 100 65 40 30 ns
t20d Delay from stop to set interrupt See Figure 8 1 1 1 1 baudrate
t21d Delay from IOR to reset interrupt 50-pF load, see Figure 8 100 65 40 30 ns
t22d Delay from stop to interrupt See Figure 14 1 1 1 1 baudrate
t23d Delay from initial IOW reset to transmit start See Figure 14 8 24 8 24 8 24 8 24 baudrate
t24d Delay from IOW to reset interrupt See Figure 14 90 60 35 25 ns
t25d Delay from stop to set RXRDY See Figure 10 and Figure 12 1 1 1 1 baudrate
t26d Delay from IOR to reset RXRDY See Figure 10 and Figure 12 100 65 40 30 ns
t27d Delay from IOW to set TXRDY See Figure 16 and 80 50 35 25 ns
t28d Delay from start to reset TXRDY See Figure 16 and 16 16 16 16 baudrate
No IOR (MODE = GND)
tRESET Reset pulse width 200 200 200 200 ns
CP CP clock period 63 42 20 20 ns
t3w Oscillator or clock speed 16 24 48 48 MHz
t6s Address setup time 70 45 30 20 ns
t6h Address hold time See Figure 3 and Figure 5 15 10 7 5 ns
t9w Read cycle delay See Figure 5 85 70 60 50 ns
t12d Delay from CS to data See Figure 5 95 65 40 25 ns
t12h Data disable time 45 30 20 15 ns
t13w IOW strobe width See Figure 3 85 70 50 40 ns
t15w Write cycle delay See Figure 3 85 70 60 50 ns
t16s Data setup time See Figure 3 75 50 30 25 ns
t16h Data hold time See Figure 3 80 50 35 25 ns
t17d Delay from CS to output 50-pF load, see Figure 6 80 50 35 25 ns
t18d Delay to set interrupt from MODEM input 50-pF load, see Figure 6 120 75 45 35 ns
t19d Delay to reset interrupt from CS 50-pF load 95 65 40 30 ns
t20d Delay from stop to set interrupt See Figure 8 1 1 1 1 baudrate
t21d Delay from IOR to reset interrupt 50-pF load, see Figure 8 85 55 40 30 ns
t22d Delay from stop to interrupt See Figure 14 1 1 1 1 baudrate
t23d Delay from initial CS reset to transmit start See Figure 14 8 24 8 24 8 24 8 24 baudrate
t24d Delay from IOW to reset interrupt See Figure 14 90 60 40 25 ns
t25d Delay from stop to set RXRDY See Figure 10 and Figure 12 1 1 1 1 baudrate
t26d Delay from CS to reset RXRDY See Figure 10 and Figure 12 95 60 35 25 ns
t27d Delay from CS to set TXRDY See Figure 16 and 80 50 35 25 ns
t28d Delay from start to reset TXRDY See Figure 16 and 16 16 16 16 baudrate
t29h IOW hold time to CS See Figure 3 and Figure 5 15 10 7 5 ns
t29s IOW setup time to CS See Figure 3 and Figure 5 70 50 30 20 ns
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