9.3.13 Programmable Baud Rate Generator with Fractional Divisor

The TL16C750E UART contains a programmable baud generator that divides reference clock by a divisor in the range between 1 and (2¹⁶ − 1) and a decimal resolution of 1/64. The output frequency of the baud rate generator is 8× or 16× the baud rate, depending on the value of DLF[7]. An additional divide-by-4 prescaler is also available and can be selected by MCR[7] as shown in the following. The formula for the divisor is:

Where 'baud divider' is either 8 or 16, depending on the value of DLF[7]. By default, DLF[7] = 0, which corresponds to a baud divider of 16 and

Figure 26 shows the internal prescaler and baud rate generator circuitry.

Figure 26. Prescaler and Baud Rate Generator Block Diagram

DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and most significant byte of the baud rate divisor. If DLL and DLH are both 0, the UART is effectively disabled, because no baud clock is generated. The programmable baud rate generator is provided to select both the transmit and receive clock rates. Table 10 and Table 11 show the baud rate and divisor correlation for the crystal with frequency 1.8432 and 3.072 MHz, respectively.

Figure 27 shows the crystal clock circuit reference.

A. For crystal with fundamental frequency from 1 to 24 MHz

B. For input clock frequency higher than 24 MHz, the crystal is not allowed and the oscillator must be used, because the TL16C750E internal oscillator cell can only support the crystal frequency up to 24 MHz.

Figure 27. Typical Crystal Clock Circuits