9.5.19 IrDA Encoder Function

Serial data from a UART is encoded to transmit data to the optoelectronics. While the serial data input to this block (Int_TX) is high, the output (TX) is always low, and the counter used to form a pulse on TX is continuously cleared. After Int_TX resets to 0, TX rises on the falling edge of the 7^th 16XCLK. On the falling edge of the 10^th 16XCLK pulse, TX falls, creating a 3-clock-wide pulse. While Int_TX stays low, a pulse is transmitted during the seventh to tenth clocks of each 16-clock bit cycle.

Figure 35. IrDA-SIR Encoding Scheme – Detailed Timing Diagram

Figure 36. Encoding Scheme – Macro View

After reset, Int_RX is high and the 4-bit counter is cleared. When a falling edge is detected on RX, Int_RX falls on the next rising edge of 16XCLK with sufficient setup time. Int_RX stays low for 16 cycles (16XCLK) and then returns to high as required by the IrDA specification. As long as no pulses (falling edges) are detected on RX, Int_RX remains high.

Figure 37. IrDA-SIR Decoding Scheme – Detailed Timing Diagram

Figure 38. IrDA-SIR Decoding Scheme – Macro View

It is possible for jitter or slight frequency differences to cause the next falling edge on RX to be missed for one 16XCLK cycle. In that case, a 1-clock-wide pulse appears on Int_RX between consecutive 0s. It is important for the UART to strobe Int_RX in the middle of the bit time to avoid latching this 1-clock-wide pulse. The TL16C750E UART already strobes incoming serial data at the proper time. Otherwise, note that data is required to be framed by a leading 0 and a trailing 1. The falling edge of that first 0 on Int_RX synchronizes the read strobe. The strobe occurs on the 8^th 16XCLK pulse after the Int_RX falling edge and once every 16 cycles thereafter until the stop bit occurs.

Figure 39. Timing Causing 1-Clock-Wide Pulse Between Consecutive Ones

Figure 40. Recommended Strobing for Decoded Data

The TL16C750E device can decode positive pulses on RX. The timing is different, but the variation is invisible to the UART. The decoder, which works from the falling edge, now recognizes a 0 on the trailing edge of the pulse rather than on the leading edge. As long as the pulse duration is fairly constant, as defined by the specification, the trailing edges should also be 16 clock cycles apart and data can readily be decoded. The 0 appears on Int_RX after the pulse rather than at the start of it.

Figure 41. Positive RX Pulse Decode – Detailed View

Figure 42. Positive RX Pulse Decode – Macro View