The PWM controller (see Figure 7-4) can be shut down by two methods: either raise the voltage at I_SENSE above 1 V or pull the COMP terminal below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output remains low until the next clock cycle after the shutdown condition at the COMP or I_SENSE terminal is removed. In one example, an externally latched shutdown can be accomplished by adding an SCR that resets by cycling V_CC below the lower UVLO threshold. At this point, the reference turns off, allowing the SCR to reset.

Figure 7-4 Shutdown Techniques

A fraction of the oscillator ramp can be summed resistively with the current-sense signal to provide slope compensation for converters requiring duty cycles over 50% (see Figure 7-5). Note that capacitor C forms a filter with R2 to suppress the leading-edge switch spikes.

Figure 7-5 Slope Compensation