ZHCSH32 November 2017 TLA2021 , TLA2022 , TLA2024
PRODUCTION DATA.
A programmable gain amplifier (PGA) is implemented before the ΔΣ ADC of the TLA2022 and TLA2024. The full-scale range is configured by bits PGA[2:0] in the configuration register and can be set to ±6.144 V, ±4.096 V, ±2.048 V, ±1.024 V, ±0.512 V, or ±0.256 V. Table 1 shows the FSR together with the corresponding LSB size. Equation 2 shows how to calculate the LSB size from the selected full-scale range.
| FSR | LSB SIZE |
|---|---|
| ±6.144 V(1) | 3 mV |
| ±4.096 V(1) | 2 mV |
| ±2.048 V | 1 mV |
| ±1.024 V | 0.5 mV |
| ±0.512 V | 0.25 mV |
| ±0.256 V | 0.125 mV |
The FSR of the TLA2021 is fixed at ±2.048 V.
Analog input voltages must never exceed the analog input voltage limits given in the Absolute Maximum Ratings table. If a VDD supply voltage greater than 4 V is used, the ±6.144-V full-scale range allows input voltages to extend up to the supply. Although in this case (or whenever the supply voltage is less than the full-scale range) a full-scale ADC output code cannot be obtained. For example, with VDD = 3.3 V and FSR = ±4.096 V, only signals up to VIN = ±3.3 V can be measured. The code range that represents voltages |VIN| > 3.3 V is not used in this case.