ZHCSP39G February 2003 – August 2022 TLC2272-Q1 , TLC2272A-Q1 , TLC2274-Q1 , TLC2274A-Q1
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics: VDD = 5 V (TLC2272-Q1 and TLC2272A-Q1)
- 6.6 Electrical Characteristics: VDD± = ±5 V (TLC2272-Q1 and TLC2272A-Q1)
- 6.7 Electrical Characteristics: VDD = 5 V (TLC2274-Q1 and TLC2274A-Q1)
- 6.8 Electrical Characteristics: VDD± = ±5 V (TLC2274-Q1 and TLC2274A-Q1)
- 6.9 Typical Characteristics
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
5 Pin Configuration and Functions
Figure 5-1 TLC2272-Q1 and
TLC2272A-Q1: D (8‑Pin SOIC) or PW (8‑Pin TSSOP) Packages, Top View
Figure 5-2 TLC2274-Q1 and
TLC2274A-Q1: D (14‑Pin SOIC) or PW (14‑Pin TSSOP) Packages, Top ViewTable 5-1 Pin Functions
| PIN | TYPE | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | NO. | |||
| TLC2272-Q1, TLC2272A-Q1 | TLC2274-Q1, TLC2274A-Q1 | |||
| 1IN+ | 3 | 3 | Input | Noninverting input, channel 1 |
| 1IN– | 2 | 2 | Input | Inverting input, channel 1 |
| 1OUT | 1 | 1 | Output | Output, channel 1 |
| 2IN+ | 5 | 5 | Input | Noninverting input, channel 2 |
| 2IN– | 6 | 6 | Input | Inverting input, channel 2 |
| 2OUT | 7 | 7 | Ouput | Output, channel 2 |
| 3IN+ | — | 10 | Input | Noninverting input, channel 3 |
| 3IN– | — | 9 | Input | Inverting input, channel 3 |
| 3OUT | — | 8 | Output | Output, channel 3 |
| 4IN+ | — | 12 | Input | Noninverting input, channel 4 |
| 4IN– | — | 13 | Input | Inverting input, channel 4 |
| 4OUT | — | 14 | Output | Output, channel 4 |
| VDD+ | 8 | 4 | Input | Positive (highest) supply |
| VDD– | 4 | 11 | Input | Negative (lowest) supply |