SLDS157E February   2008  – December 2014 TLC59116

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Open-Circuit Detection
      2. 9.3.2 Overtemperature Detection and Shutdown
      3. 9.3.3 Power-On Reset (POR)
      4. 9.3.4 External Reset
      5. 9.3.5 Software Reset
      6. 9.3.6 Individual Brightness Control With Group Dimming/Blinking
    4. 9.4 Device Functional Modes
      1. 9.4.1 Active
      2. 9.4.2 Standby
    5. 9.5 Register Maps
      1. 9.5.1  Mode Register 1 (MODE1)"SLEEP" to "OSC" in Mode Register 1 (MODE1) Table.
      2. 9.5.2  Mode Register 2 (MODE2)
      3. 9.5.3  Brightness Control Registers 0 to 15 (PWM0 to PWM15)
      4. 9.5.4  Group Duty Cycle Control Register (GRPPWM)
      5. 9.5.5  Group Frequency Register (GRPFREQ)
      6. 9.5.6  LED Driver Output State Registers 0 to 3 (LEDOUT0 to LEDOUT3)
      7. 9.5.7  I2C Bus Subaddress Registers 1 to 3 (SUBADR1 to SUBADR3)
      8. 9.5.8  LED All Call I2C Bus Address Register (ALLCALLADR)
      9. 9.5.9  Output Gain Control Register (IREF)
      10. 9.5.10 Error Flags Registers (EFLAG1, EFLAG2)
      11. 9.5.11 Control Register
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Device Address
      2. 10.1.2 Regular I2C Bus Slave Address
      3. 10.1.3 LED All Call I2C Bus Address
      4. 10.1.4 LED Sub Call I2C Bus Address
      5. 10.1.5 Software Reset I2C Bus Address
      6. 10.1.6 Characteristics of the I2C Bus
        1. 10.1.6.1 Bit Transfer
        2. 10.1.6.2 Start and Stop Conditions
        3. 10.1.6.3 Acknowledge
      7. 10.1.7 System Configuration
      8. 10.1.8 Constant Current Output
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Adjusting Output Current
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage 0 7 V
VI Input voltage –0.4 VCC + 0.4 V
VO Output voltage –0.5 20 V
IO Output current per channel 120 mA
TJ Junction temperature –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –55 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 1500 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

All unused inputs of the device must be held at VCC or GND to ensure proper device operation
MIN MAX UNIT
VCC Supply voltage 3 5.5 V
VIH High-level input voltage SCL, SDA, RESET, A0, A1, A2, A3 0.7 × VCC VCC V
VIL Low-level input voltage SCL, SDA, RESET, A0, A1, A2, A3 0 0.3 × VCC V
VO Supply voltage to output pins OUT0 to OUT15 17 V
IOL Low-level output current sink SDA VCC = 3 V 20 mA
VCC = 5 V 30
IO Output current per channel OUT0 to OUT15 5 120 mA
TA Operating free-air temperature –40 85 °C

7.4 Thermal Information

THERMAL METRIC(1) TLC59116 UNIT
PW RHB
28 PINS 32 PINS
RθJA Junction-to-ambient thermal resistance 78 34.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 18.8 26.3
RθJB Junction-to-board thermal resistance 36 8.3
ψJT Junction-to-top characterization parameter 0.5 0.4
ψJB Junction-to-board characterization parameter 35.5 8.2
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 3.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

VCC = 3 V to 5.5 V, TA = –40 °C to 85 °C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
II Input / output leakage current SCL, SDA, A0, A1, A2, A3, RESET VI = VCC or GND ±0.3 μA
Output leakage current OUT0 to OUT15 VO = 17 V, TJ = 25°C 0.5 μA
VPOR Power-on reset voltage 2.5 V
IOL Low-level output current SDA VCC = 3 V, VOL = 0.4 V 20 mA
VCC = 5 V, VOL = 0.4 V 30
IO(1) Output current 1 OUT0 to OUT15 VO = 0.6 V, Rext = 720 Ω, CG = 0.992(3) 26 mA
Output current error OUT0 to OUT15 IO = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C ±8%
Output channel to channel current error OUT0 to OUT15 IO = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C ±6%
IO(2) Output current 2 OUT0 to OUT15 VO = 0.8 V, Rext = 360 Ω, CG = 0.992(3) 52 mA
Output current error OUT0 to OUT15 IO = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C ±8%
Output channel to channel current error OUT0 to OUT15 IO = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C ±6%
IOUT vs VOUT Output current vs output voltage regulation OUT0 to OUT15 VO = 1 V to 3 V, IO = 26 mA ±0.1 %/V
VO = 3 V to 5.5 V, IO = 26 mA to 120 mA ±1
IOUT,Th1 Threshold current 1 for error detection OUT0 to OUT15 IOUT,target = 26 mA 0.5 × ITARGET%
IOUT,Th2 Threshold current 2 for error detection OUT0 to OUT15 IOUT,target = 52 mA 0.5 × ITARGET%
IOUT,Th3 Threshold current 3 for error detection OUT0 to OUT15 IOUT,target = 104 mA 0.5 × ITARGET%
TSD Overtemperature shutdown(2) 150 175 200 °C
THYS Restart hysteresis 15 °C
Ci Input capacitance SCL, A0, A1, A2, A3, RESET VI = VCC or GND 5 pF
Cio Input / output capacitance SDA VI = VCC or GND 8 pF
ICC Supply current VCC = 5.5 V OUT0 to OUT15 = OFF, Rext = Open 25 mA
OUT0 to OUT15 = OFF, Rext = 720 Ω 29
OUT0 to OUT15 = OFF, Rext = 360 Ω 32
OUT0 to OUT15 = OFF, Rext = 180 Ω 37
OUT0 to OUT15 = ON, Rext = 720 Ω 29
OUT0 to OUT15 = ON, Rext = 360 Ω 32
OUT0 to OUT15 = ON, Rext = 180 Ω 37
(1) All typical values are at TA = 25 °C.
(2) Specified by design
(3) CG is the Current Gain and is defined in Table 12.

7.6 Timing Requirements

TA = –40 °C to 85 °C
STANDARD MODE
I2C BUS		 FAST MODE
I2C BUS		 FAST MODE PLUS
I2C BUS		 UNIT
MIN MAX MIN MAX MIN MAX
I2C INTERFACE
fSCL SCL clock frequency(1) 0 100 0 400 0 1000 kHz
tBUF I2C bus free time between Stop and Start conditions 4.7 1.3 0.5 μs
tHD;STA Hold time (repeated) Start condition 4 0.6 0.26 μs
tSU;STA Set-up time for a repeated Start condition 4.7 0.6 0.26 μs
tSU;STO Set-up time for Stop condition 4 0.6 0.26 μs
tHD;DAT Data hold time 0 0 0 ns
tVD;ACK Data valid acknowledge time(2) 0.3 3.45 0.1 0.9 0.05 0.45 μs
tVD;DAT Data valid time(3) 0.3 3.45 0.1 0.9 0.05 0.45 μs
tSU;DAT Data set-up time 250 100 50 ns
tLOW Low period of SCL clock 4.7 1.3 0.5 μs
tHIGH High period of SCL clock 4 0.6 0.26 μs
tf Fall time of both SDA and SCL signals(5)(6) 300 20+0.1Cb(4) 300 120 ns
tr Rise time of both SDA and SCL signals 1000 20+0.1Cb(4) 300 120 ns
tSP Pulse width of spikes that must be suppressed by the input filter(7) 50 50 50 ns
RESET
tW Reset pulse width 10 10 10 ns
tREC Reset recovery time 0 0 0 ns
tRESET Time to reset(8)(9) 400 400 400 ns
(1) Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held low for a minimum of 25 ms. Disable bus time-out feature for dc operation.
(2) tVD;ACK = time for ACK signal from SCL low to SDA (out) low.
(3) tVD;DAT = minimum time for SDA data out to be valid following SCL low.
(4) Cb = Total capacitance of one bus line in pF
(5) A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region of the SCL falling edge.
(6) The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
(7) Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
(8) Resetting the device while actively communicating on the bus may cause glitches or errant Stop conditions.
(9) Upon reset, the full delay will be the sum of tRESET and the RC time constant of the SDA bus.

7.7 Typical Characteristics

g_iout_rext_lds157.gifFigure 1. IOUT,target vs Rext
g_iout_vout_lds157.gifFigure 2. Output Current vs Output Voltage
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