SLVS677C July   2008  – October 2015 TLC5926 , TLC5927

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: VDD = 3 V
    6. 7.6  Electrical Characteristics: VDD = 5.5 V
    7. 7.7  Timing Recommendations
    8. 7.8  Switching Characteristics: VDD = 3 V
    9. 7.9  Switching Characteristics: VDD = 5.5 V
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Open-Circuit Detection Principle
      2. 9.3.2 Short-Circuit Detection Principle (TLC5927 Only)
      3. 9.3.3 Overtemperature Detection and Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation Mode Switching
      2. 9.4.2 Normal Mode Phase
      3. 9.4.3 Special Mode Phase
        1. 9.4.3.1 Reading Error Status Code in Special Mode
      4. 9.4.4 Writing Configuration Code in Special Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Constant Current
      2. 10.1.2 Adjusting Output Current
      3. 10.1.3 16-Bit Configuration Code and Current Gain
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD Supply voltage 0 7 V
VI Input voltage –0.4 VDD + 0.4 V
VO Output voltage –0.5 20 V
IOUT Output current 120 mA
IGND GND terminal current 1920 mA
TA Free-air operating temperature range –40 125 °C
TJ Operating junction temperature range –40 150 °C
Tstg Storage temperature range –55 150 °C

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS MIN MAX UNIT
VDD Supply voltage 3 5.5 V
VO Supply voltage to the output pins OUT0–OUT15 17 V
IO Output current DC test circuit VO ≥ 0.6 V 5 mA
VO ≥ 1 V 120
IOH High-level output current SDO –1 mA
IOL Low-level output current SDO 1 mA
VIH High-level input voltage CLK, OE(ED2), LE(ED1), and SDI 0.7 × VDD VDD V
VIL Low-level input voltage CLK, OE(ED2), LE(ED1), and SDI 0 0.3 × VDD V

7.4 Thermal Information

THERMAL METRIC (1) TLC5926, TLC5927 UNIT
DBQ (SSOP) DW (SOIC) PWP (HTSSOP)
24 PINS 24 PINS 24 PINS
RθJA Junction-to-ambient thermal resistance (Mounted on JEDEC 1-layer board (JESD 51-3), No airflow) 99.8 80.5 63.9 °C/W
Junction-to-ambient thermal resistance (Mounted on JEDEC 4-layer board (JESD 51-7), No airflow) 61 45.5 42.7 °C/W
Junction-to-ambient thermal resistance (Mounted on JEDEC 4-layer board (JESD 51-5), No airflow) - - 34.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 49.6 40.8 23.9 °C/W
RθJB Junction-to-board thermal resistance 38 40.5 21.6 °C/W
ψJT Junction-to-top characterization parameter 13.5 18 0.8 °C/W
ψJB Junction-to-board characterization parameter 37.7 40.2 21.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance - - 5.5 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics: VDD = 3 V

VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VO Supply voltage to the output pins 17 V
IO Output current VO ≥ 0.6 V 5 mA
VO ≥ 1 V 120
VIH High-level input voltage 0.7 × VDD VDD V
VIL Low-level input voltage GND 0.3 × VDD
Ileak Output leakage current VOH = 17 V TJ = 25°C 0.5 μA
TJ = 125°C 1
VOH High-level output voltage SDO, IOL = –1 mA VDD – 0.4 V
VOL Low-level output voltage SDO, IOH = 1 mA 0.4 V
IO(1) Output current 1 VOUT = 0.6 V, Rext = 720 Ω, CG = 0.992 26 mA
Output current error, die-die IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C ±6%
Output current error, channel-to-channel IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C ±6%
IO(2) Output current 2 VO = 0.8 V, Rext = 360 Ω, CG = 0.992 52 mA
Output current error, die-die IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C ±6%
Output current error, channel-to-channel IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C ±6%
IOUT vs VOUT Output current vs output voltage regulation VO = 1 V to 3  V, IO = 26 mA ±0.1 %/V
IOUT vs VDD Output current vs supply voltage VDD = 3.0 V to 5.5 V, IO = 26 mA/120 mA ±1
Pullup resistance OE(ED2) 250 500 800 kΩ
Pulldown resistance LE(ED1) 250 500 800 kΩ
Tsd Overtemperature shutdown(1) 150 175 200 °C
Thys Restart temperature hysteresis 15 °C
IOUT,Th Threshold current for open error detection IOUT,target = 5 mA to 120 mA 0.5% × Itarget
VOUT,TTh Trigger threshold voltage for short-error detection (TLC5927 only) IOUT,target = 5 mA to 120 mA 2.4 2.6 3.1 V
VOUT, RTh Return threshold voltage for short-error detection (TLC5927 only) IOUT,target = 5 mA to 120 mA 2.2 V
IDD Supply current OUT0–OUT15 = off, Rext = Open, OE = VIH 10 mA
OUT0–OUT15 = off, Rext = 720 Ω, OE = VIH 14
OUT0–OUT15 = off, Rext = 360 Ω, OE = VIH 18
OUT0–OUT15 = off, Rext = 180 Ω, OE = VIH 20
OUT0–OUT15 = on, Rext = 720 Ω, OE = VIL 14
OUT0–OUT15 = on, Rext = 360 Ω, OE = VIL 18
OUT0–OUT15 = on, Rext = 180 Ω, OE = VIL 20
(1) Specified by design

7.6 Electrical Characteristics: VDD = 5.5 V

VDD = 5.5 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VO Supply voltage to the output pins 17 V
IO Output current VO ≥ 0.6 V 5 mA
VO ≥ 1 V 120
VIH High-level input voltage 0.7 × VDD VDD V
VIL Low-level input voltage GND 03 × VDD
Ileak Output leakage current VOH = 17 V TJ = 25°C 0.5 μA
TJ = 125°C 1
VOH High-level output voltage SDO, IOL = –1 mA VDD – 0.4 V
VOL Low-level output voltage SDO, IOH = 1 mA 0.4 V
IO(1) Output current 1 VOUT = 0.6 V, Rext = 720 Ω, CG = 0.992 26 mA
Output current error, die-die IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C ±6%
Output current error, channel-to-channel IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C ±6%
IO(2) Output current 2 VO = 0.8 V, Rext = 360 Ω, CG = 0.992 52 mA
Output current error, die-die IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C ±6%
Output current error, channel-to-channel IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C ±6%
IOUT vs VOUT Output current vs output voltage regulation VO = 1 V to 3 V , IO = 26 mA ±0.1 %/V
IOUT vs VDD Output current vs supply voltage VDD = 3.0 V to 5.5 V, IO = 26 mA/120 mA ±1
Pullup resistance OE(ED2), 250 500 800 kΩ
Pulldown resistance LE(ED1), 250 500 800 kΩ
Tsd Over temperature shutdown(1) 150 175 200 °C
Thys Restart temperature hysteresis 15 °C
IOUT,Th Threshold current for open error detection IOUT,target = 5 mA to 120 mA 0.5% × Itarget
VOUT,TTh Trigger threshold voltage for short-error detection (TLC5927 only) IOUT,target = 5 mA to 120 mA 2.4 2.6 3.1 V
VOUT, RTh Return threshold voltage for short-error detection (TLC5927 only) IOUT,target = 5 mA to 120 mA 2.2 V
IDD Supply current OUT0–OUT15 = off, Rext = Open, OE = VIH 11 mA
OUT0–OUT15 = off, Rext = 720 Ω, OE = VIH 17
OUT0–OUT15 = off, Rext = 360 Ω, OE = VIH 18
OUT0–OUT15 = off, Rext = 180 Ω, OE = VIH 25
OUT0–OUT15 = on, Rext = 720 Ω, OE = VIL 17
OUT0–OUT15 = on, Rext = 360 Ω, OE = VIL 18
OUT0–OUT15 = on, Rext = 180 Ω, OE = VIL 25
(1) Specified by design

7.7 Timing Recommendations

VDD = 3 V to 5.5 V (unless otherwise noted)
MIN MAX UNIT
tw(L) LE(ED1) pulse duration Normal mode 20 ns
tw(CLK) CLK pulse duration Normal mode 20 ns
tw(OE) OE(ED2) pulse duration Normal mode 1000 ns
tsu(D) Setup time for SDI Normal mode 7 ns
th(D) Hold time for SDI Normal mode 3 ns
tsu(L) Setup time for LE(ED1) Normal mode 18 ns
th(L) Hold time for LE(ED1) Normal mode 18 ns
tw(CLK) CLK pulse duration Error Detection mode 20 ns
tw(ED2) OE(ED2) pulse duration Error Detection mode 2000 ns
tsu(ED1) Setup time for LE(ED1) Error Detection mode 7 ns
th(ED1) Hold time for LE(ED1) Error Detection mode 10 ns
tsu(ED2) Setup time for OE(ED2) Error Detection mode 7 ns
th(ED2) Hold time for OE(ED2) Error Detection mode 10 ns
fCLK Clock frequency Cascade operation, VDD = 3 V to 5.5 V 30 MHz

7.8 Switching Characteristics: VDD = 3 V

VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH1 Low-to-high propagation delay time, CLK to OUTn VIH = VDD, VIL = GND, Rext = 360 Ω, VL = 4 V, RL = 44 Ω, CL = 70 pF, CG = 0.992 35 65 105 ns
tPLH2 Low-to-high propagation delay time, LE(ED1) to OUTn 35 65 105 ns
tPLH3 Low-to-high propagation delay time, OE(ED2) to OUTn 35 65 105 ns
tPLH4 Low-to-high propagation delay time, CLK to SDO 20 45 ns
tPHL1 High-to-low propagation delay time, CLK to OUTn 200 300 470 ns
tPHL2 High-to-low propagation delay time, LE(ED1) to OUTn 200 300 470 ns
tPHL3 High-to-low propagation delay time, OE(ED2) to OUTn 200 300 470 ns
tPHL4 High-to-low propagation delay time, CLK to SDO 20 40 ns
tw(CLK) Pulse duration, CLK 20 ns
tw(L) Pulse duration LE(ED1) 20 ns
tw(OE) Pulse duration, OE(ED2) 1000 ns
tw(ED2) Pulse duration, OE(ED2) in Error Detection mode 2 μs
th(ED1,ED2) Hold time, LE(ED1), and OE(ED2) 10 ns
th(D) Hold time, SDI 5 ns
tsu(D,ED1,ED2) Setup time, SDI, LE(ED1), and OE(ED2) 7 ns
th(L) Hold time, LE(ED1), Normal mode 18 ns
tsu(L) Setup time, LE(ED1), Normal mode 18 ns
tr Rise time, CLK (1) 500 ns
tf Fall time, CLK (1) 500 ns
tor Rise time, outputs (off) 245 ns
tof Rise time, outputs (on) 600 ns
fCLK Clock frequency Cascade operation 30 MHz
(1) If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices.

7.9 Switching Characteristics: VDD = 5.5 V

VDD = 5.5 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH1 Low-to-high propagation delay time, CLK to OUTn VIH = VDD, VIL = GND, Rext = 360 Ω, VL = 4 V, RL = 44 Ω, CL = 70 pF, CG = 0.992 27 65 95 ns
tPLH2 Low-to-high propagation delay time, LE(ED1) to OUTn 27 65 95 ns
tPLH3 Low-to-high propagation delay time, OE(ED2) to OUTn 27 65 95 ns
tPLH4 Low-to-high propagation delay time, CLK to SDO 20 30 ns
tPHL1 High-to-low propagation delay time, CLK to OUTn 180 300 445 ns
tPHL2 High-to-low propagation delay time, LE(ED1) to OUTn 180 300 445 ns
tPHL3 High-to-low propagation delay time, OE(ED2) to OUTn 180 300 445 ns
tPHL4 High-to-low propagation delay time, CLK to SDO 20 30 ns
tw(CLK) Pulse duration, CLK 20 ns
tw(L) Pulse duration LE(ED1) 20 ns
tw(OE) Pulse duration, OE(ED2) 1000 ns
tw(ED2) Pulse duration, OE(ED2) in Error Detection mode 2 μs
th(ED1,ED2) Hold time, LE(ED1), and OE(ED2) 10 ns
th(D) Hold time, SDI 3 ns
tsu(D,ED1,ED2) Setup time, SDI, LE(ED1), and OE(ED2) 4 ns
th(L) Hold time, LE(ED1), Normal mode 15 ns
tsu(L) Setup time, LE(ED1), Normal mode 15 ns
tr Rise time, CLK (1) 500 ns
tf Fall time, CLK (1) 500 ns
tor Rise time, outputs (off) 245 ns
tof Rise time, outputs (on) 570 ns
fCLK Clock frequency Cascade operation 30 MHz
(1) If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices.

7.10 Typical Characteristics

Figure 1: At low voltage levels (VO), the output current (IO) may be limited. Figure 1 shows the dependency of the output current on the output voltage.
TLC5926 TLC5927 g_io_vo_lvs677.gif Figure 1. Output Current vs Output Voltage
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |