11.1 Layout Guidelines

1. Place the decoupling capacitor near the VCC pin and GND plane.
2. Place the current programming resistor Riref close to IREF pin and IREFGND pin.
3. Route the GND pattern as widely as possible for large GND currents.
4. Routing wire between the LED cathode side and the device OUTn pin should be as short and straight as possible to reduce wire inductance.
5. When several ICs are chained, symmetric placements are recommended.

11.2 Layout Example

Figure 24. Layout Recommendation

11.3 Power Dissipation Calculation

The device power dissipation must be below the power dissipation rating of the device package to ensure correct operation. Equation 10 calculates the power dissipation of device.

Equation 10.

where

• V_CC: device supply voltage
• I_CC: device supply current
• V_OUT: TLC5940 OUTn voltage when driving LED current
• I_MAX: LED current adjusted by R_(IREF) Resistor
• DC_n: maximum dot correction value for OUTn
• N: number of OUTn driving LED at the same time
• d_PWM: duty cycle defined by BLANK pin or GS PWM value