9.2.2.3.1 Data Write and PWM Control with Internal Grayscale Clock Mode

When the EXTCLK bit is 0, the internal oscillator clock is used for PWM control of OUTXn (X = R/G/B and n = 0-3) as the GS reference clock. This mode is ideal for illumination applications that change the display image at low frequencies. The data and clock timing is shown in Figure 3 and Figure 34. A writing procedure for the function setting and display control follows:

1. Power up VCC (VLED); all OUTXn are off because BLANK is set to 1.
2. Write the 224-bit data packet (with MSB bit first) for the Nth TLC5971 using the SDTI and SCKI signals. The first six bits of the 224-bit data packet are used as the write command. The write command must be 25h (100101b); otherwise, the 218-bit data in the 224-bit shift register are not copied to the 218-bit data latch. The EXTCLK bit must be set to 0 for the internal oscillator mode. Also, the DSPRPT bit should be set to 1 to repeat the PWM timing control and BLANK set to 0 to start the PWM control.
3. Write the 224-bit data packet for the (N – 1) TLC5971 without delay after step 2.
4. Repeat the data write sequence until all TLC5971s have data. The total shift clock count (SCKI) is now 224 × N. After all device data are written, stop the SCKI at a high or low level for 8× the period between the last SCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift resister are copied to the 218-bit data latch in all devices and the PWM control is started or updated at the same time.

Figure 34. Data Packet and Display Start/Update Timing 1 (Internal Oscillator Mode)

9.2.2.3.2 Data Write and PWM Control with External Grayscale Clock Mode

When the EXTCLK bit is 1, the data shift clock (SCKI) is used for PWM control of OUTXn (X = R/G/B and n = 0-3) as the GS reference clock. This mode is ideal for video image applications that change the display image with high frequencies or for certain display applications that must synchronize all TLC5971s. The data and clock timing are shown in Figure 3 and Figure 35. A writing procedure for the display data and display timing control follows:

1. Power up VCC (VLED); all OUTXn are off because BLANK is set to 1.
2. Write the 224-bit data packet MSB-first for the Nth TLC5971 using the SDTI and SCKI signals. The first six bits of the 224-bit data packet are used as the write command. The write command must be 25h (100101b); otherwise, the 218-bit data in the 224-bit shift register are not copied to the 218-bit data latch. The EXTCLK bit must be set to 1 for the external oscillator mode. Also, the DSPRPT bit should be set to 0 so that the PWM control is not repeated, the TMGRST bit should be set to 1 to reset the PWM control timing at the internal latch pulse generation, and BLANK must be set to 0 to start the PWM control.
3. Write the 224-bit data for the (N – 1) TLC5971 without delay after step 2.
4. Repeat the data write sequence until all TLC5971s have data. The total shift clock count (SCKI) is 224 × N. After all device data are written, stop the SCKI at a high or low level for 8× the period between the last SCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift resister are copied to the 218-bit data latch in all devices.
5. To start the PWM control, send one pulse of the SCKI clock with SDTI low after 1.34 µs or more from step 4. The OUTXn are turned on when the output GS data are not 0000h.
6. Send the remaining 65535 SCKI clocks with SDTI low. Then the PWM control for OUTXn is synchronized with the SCKI clock and one display period is finished with a total of 65536 SCKI clock periods.
7. Repeat step 2 to step 6 for the next display period.

Figure 35. Data Packet and Display Start/Update Timing 2 (External Clock Mode)

There is another control procedure that is recommended for a long chain of cascaded devices. The data and clock timings are shown in Figure 3 and Figure 36. When 256 TLC5971 units are cascaded, use the following procedure:

1. Power up VCC (VLED); all OUTXn are off because BLANK is set to 1.
2. Write the 224-bit data packet MSB-first for the 256th TLC5971 using the SDTI and SCKI signals. The EXTCLK bit must be set to 1 for the external oscillator mode. Also, the DSPRPT bit should be set to 0 so that the PWM control does not repeat, the TMGRST bit should be set to 1 to reset the PWM control timing with the internal latch pulse, and BLANK must be set to 0 to start the PWM control.
3. Repeat the data write sequence for all TLC5971s. The total shift clock count (SCKI) is 57344 (224 × 256). After all device data are written, stop the SCKI signal at a high or low level for eight or more periods between the last SCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift resister are copied to the 218-bit data latch in all devices.
4. To control the PWM, send 8192 SCKI clock periods with SDTI low after 1.34 µs or more from step 3 (or step 7). These 8192 clock periods are used for the OUTXn PWM control.
5. Write the new 224-bit data packets to the 256th to first TLC5971s for the next display with 256 × 224 SCKI clock for a total of 57344 clocks. The PWM control for OUTXn remains synchronized with the SCKI clock and one display period is finished with a total of 65536 SCKI clocks. The SCKI clock signal is therefore used for PWM control and, at the same time, to write data into the shift registers of all cascaded parts.
6. Stop the SCKI signal at a high or low level for eight or more periods between the last SCKI rising edge and the second to last SCKI rising edge. Then the 218-bit LSBs in the 224-bit shift resister are copied to the 218-bit data latch in all devices.
7. Repeat step 4 to step 6 for the next display periods.

Figure 36. Data Packet and Display Start/Update Timing 3
(External Clock Mode With 256 Cascaded Devices)