ZHCSPI8D November 2021 – July 2022 TLC6984
PRODUCTION DATA
The internal GCLK frequency is configured by the Frequency Multiplier (FREQ_MUL), and is determined by the PWM resolution. The GCLK frequency can be calculated by the below equations:
where
Table 9-2 gives the values based on the system configuration and equation.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
Nsub_period | 32 |
Nscan_line | 30 |
TSW | 1.5 µs |
Tblank | 0 |
NGCLK_seg | 512 |
GSmax | 16383 |
fGCLK | 71.3 MHz |
Considering SCLK frequency and FREQ_MUL, the SCLK can be 13.9 MHz, and FREQ_MUL can be 6. So the GCLK is 83.4 MHz.