ZHCSEM2A August   2015  – August 2015 TLC6C5712-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power-On Reset (POR)
        1. 7.3.1.1 Start-Up or UVLO POR
        2. 7.3.1.2 Software POR
        3. 7.3.1.3 Reset POR
        4. 7.3.1.4 POR Masking
      2. 7.3.2 Error Feedback
        1. 7.3.2.1 Recovery From Error
        2. 7.3.2.2 RESET_STATUS Command
      3. 7.3.3 PWM Input
        1. 7.3.3.1 PWM Dimming
        2. 7.3.3.2 PWM Monitor
        3. 7.3.3.3 PWM Mapping
        4. 7.3.3.4 PWM MAP Register Lock
      4. 7.3.4 Constant-Current Output
        1. 7.3.4.1 Global Current Reference
        2. 7.3.4.2 Current Reference Monitor and Protection
        3. 7.3.4.3 Channel Activation Control
        4. 7.3.4.4 Individual Dot Correction Control
        5. 7.3.4.5 Output Slew-Rate Adjustment
        6. 7.3.4.6 Register Lock
        7. 7.3.4.7 Deactivated-Channel Internal Pullup
      5. 7.3.5 Advanced Diagnostics
        1. 7.3.5.1 Pre-Thermal Warning and Thermal Shutdown Protection
        2. 7.3.5.2 LED Short-to-Supply Detection
        3. 7.3.5.3 LED Short-to-GND Detection
        4. 7.3.5.4 LED Open-Load Detection
        5. 7.3.5.5 Deactivated-Channel LED Open or Short Detection
        6. 7.3.5.6 Weak LED Supply (WLS) Detection
          1. 7.3.5.6.1 Adjacent-Pin Short Detection
          2. 7.3.5.6.2 Force Error
          3. 7.3.5.6.3 Reference Resistor Open and Short Detection
          4. 7.3.5.6.4 PWM Monitor
      6. 7.3.6 Register Protection
        1. 7.3.6.1 Dot Correction Register Lock and Unlock
        2. 7.3.6.2 PWM Mapping Register Lock and Unlock
        3. 7.3.6.3 Masking Register Lock and Unlock
        4. 7.3.6.4 Miscellaneous Register Lock and Unlock
        5. 7.3.6.5 Lock Flag Indication
      7. 7.3.7 Serial Interface - SPI
      8. 7.3.8 Thermal Information
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VCC < 2.8 V (Power-On-Reset Threshold)
      2. 7.4.2 Operation With VCC ≥ 2.8 V (Power-On-Reset Threshold)
    5. 7.5 Register Maps
      1. 7.5.1  WRITE_MAP0 Register (address = 40h) [reset = 00h]
      2. 7.5.2  WRITE_MAP1 Register (address = 41h) [reset = 00h]
      3. 7.5.3  WRITE_MAP2 Register (address = 42h) [reset = 00h]
      4. 7.5.4  WRITE_MAP3 Register (address = 43h) [reset = 00h]
      5. 7.5.5  WRITE_MAP4 Register (address = 44h) [reset = 00h]
      6. 7.5.6  WRITE_MAP5 Register (address = 45h) [reset = 00h]
      7. 7.5.7  WRITE_CORR0 Register (address = 46h) [reset = 00h]
      8. 7.5.8  WRITE_CORR1 Register (address = 47h) [reset = 00h]
      9. 7.5.9  WRITE_CORR2 Register (address = 48h) [reset = 00h]
      10. 7.5.10 WRITE_CORR3 Register (address = 49h) [reset = 00h]
      11. 7.5.11 WRITE_CORR4 Register (address = 4Ah) [reset = 00h]
      12. 7.5.12 WRITE_CORR5 Register (address = 4Bh) [reset = 00h]
      13. 7.5.13 WRITE_CORR6 Register (address = 4Ch) [reset = 00h]
      14. 7.5.14 WRITE_CORR7 Register (address = 4Dh) [reset = 00h]
      15. 7.5.15 WRITE_CORR8 Register (address = 4Eh) [reset = 00h]
      16. 7.5.16 WRITE_CORR9 Register (address = 4Fh) [reset = 00h]
      17. 7.5.17 WRITE_CORR10 Register (address = 50h) [reset = 00h]
      18. 7.5.18 WRITE_CORR11 Register (address = 51h) [reset = 00h]
      19. 7.5.19 WRITE_CH_ON_MASK0 Register (address = 52h) [reset = 3Fh]
      20. 7.5.20 WRITE_CH_ON_MASK1 Register (address = 53h) [reset = 3Fh]
      21. 7.5.21 WRITE_SHORT_MASK0 Register (address = 54h) [reset = 3Fh]
      22. 7.5.22 WRITE_SHORT_MASK1 Register (address = 55h) [reset = 3Fh]
      23. 7.5.23 WRITE_SHORT_GND_MASK0 Register (address = 56h) [reset = 3Fh]
      24. 7.5.24 WRITE_SHORT_GND_MASK1 Register (address = 57h) [reset = 3Fh]
      25. 7.5.25 WRITE_OPEN_MASK0 Register (address = 58h) [reset = 3Fh]
      26. 7.5.26 WRITE_OPEN_MASK1 Register (address = 59h) [reset = 3Fh]
      27. 7.5.27 WRITE_PWM_FAULT_MASK Register (address = 60h) [reset = 3Fh]
      28. 7.5.28 RESET_POR Register (address = 61h) [reset = 00h]
      29. 7.5.29 RESET_STATUS Register (address = 62h) [reset = 00h]
      30. 7.5.30 SOFTWARE_POR Register (address = 63h) [reset = 00h]
      31. 7.5.31 WRITE_DIS_PULL_UP_0 Register (address = 64h) [reset = 00h]
      32. 7.5.32 WRITE_DIS_PULL_UP_1 Register (address = 65h) [reset = 00h]
      33. 7.5.33 WRITE_ERROR_MASK Register (address = 66h) [reset = 00h]
      34. 7.5.34 WRITE_MISC_CMD Register (address = 67h) [reset = 00h]
      35. 7.5.35 LOCK_MAP Register (address = 68h) [reset = 00h]
      36. 7.5.36 LOCK_CORR Register (address = 69h) [reset = 00h]
      37. 7.5.37 LOCK_MASK Register (address = 6Ah) [reset = 00h]
      38. 7.5.38 LOCK_MISC Register (address = 6Bh) [reset = 00h]
      39. 7.5.39 UNLOCK_MAP Register (address = 6Ch) [reset = 00h]
      40. 7.5.40 UNLOCK_CORR Register (address = 6Dh) [reset = 00h]
      41. 7.5.41 UNLOCK_MASK Register (address = 6Eh) [reset = 00h]
      42. 7.5.42 UNLOCK_MISC Register (address = 6Fh) [reset = 00h]
      43. 7.5.43 READ_MAP0 Register (address = 80h) [reset = 00h]
      44. 7.5.44 READ_MAP1 Register (address = 81h) [reset = 00h]
      45. 7.5.45 READ_MAP2 Register (address = 82h) [reset = 00h]
      46. 7.5.46 READ_MAP3 Register (address = 83h) [reset = 00h]
      47. 7.5.47 READ_MAP4 Register (address = 84h) [reset = 00h]
      48. 7.5.48 READ_MAP5 Register (address = 85h) [reset = 00h]
      49. 7.5.49 READ_CORR0 Register (address = 86h) [reset = 00h]
      50. 7.5.50 READ_CORR1 Register (address = 87h) [reset = 00h]
      51. 7.5.51 READ_CORR2 Register (address = 88h) [reset = 00h]
      52. 7.5.52 READ_CORR3 Register (address = 89h) [reset = 00h]
      53. 7.5.53 READ_CORR4 Register (address = 8Ah) [reset = 00h]
      54. 7.5.54 READ_CORR5 Register (address = 8Bh) [reset = 00h]
      55. 7.5.55 READ_CORR6 Register (address = 8Ch) [reset = 00h]
      56. 7.5.56 READ_CORR7 Register (address = 8Dh) [reset = 00h]
      57. 7.5.57 READ_CORR8 Register (address = 8Eh) [reset = 00h]
      58. 7.5.58 READ_CORR9 Register (address = 8Fh) [reset = 00h]
      59. 7.5.59 READ_CORR10 Register (address = 90h) [reset = 00h]
      60. 7.5.60 READ_CORR11 Register (address = 91h) [reset = 00h]
      61. 7.5.61 READ_CH_ON_MASK0 Register (address = 92h) [reset = 3Fh]
      62. 7.5.62 READ_CH_ON_MASK1 Register (address = 93h) [reset = 3Fh]
      63. 7.5.63 READ_SHORT_MASK0 Register (address = 94h) [reset = 3Fh]
      64. 7.5.64 READ_SHORT_MASK1 Register (address = 95h) [reset = 3Fh]
      65. 7.5.65 READ_SHORT_GND_MASK0 Register (address = 96h) [reset = 3Fh]
      66. 7.5.66 READ_SHORT_GND_MASK1 Register (address = 97h) [reset = 3Fh]
      67. 7.5.67 READ_OPEN_MASK0 Register (address = 98h) [reset = 3Fh]
      68. 7.5.68 READ_OPEN_MASK1 Register (address = 99h) [reset = 3Fh]
      69. 7.5.69 READ_SHORT_FAULT0 (address = 9Ah) [reset = 00h]
      70. 7.5.70 READ_SHORT_FAULT1 (address = 9Bh) [reset = 00h]
      71. 7.5.71 READ_SHORT_GND_FAULT0 (address = 9Ch) [reset = 00h]
      72. 7.5.72 READ_SHORT_GND_FAULT1 (address = 9Dh) [reset = 00h]
      73. 7.5.73 READ_OPEN_FAULT0 (address = 9Eh) [reset = 00h]
      74. 7.5.74 READ_OPEN_FAULT1 (address = 9Fh) [reset = 00h]
      75. 7.5.75 READ_PWM_FAULT_MASK Register (address = A1h) [reset = 3Fh]
      76. 7.5.76 READ_STATUS0 (address = A2h) [reset = 40h]
      77. 7.5.77 READ_STATUS1 (address = A3h) [reset = 00h]
      78. 7.5.78 READ_DIS_PULL_UP_0 Register (address = A4h) [reset = 00h]
      79. 7.5.79 READ_DIS_PULL_UP_1 Register (address = A5h) [reset = 00h]
      80. 7.5.80 READ_ERROR_MASK (address = A6h) [reset = 00h]
      81. 7.5.81 READ_MISC_CMD Register (address = A7h) [reset = 00h]
      82. 7.5.82 READ_ADSHORT0 (address = A8h) [reset = 00h]
      83. 7.5.83 READ_ADSHORT1 (address = A9h) [reset = 00h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Multiple Devices Connected in Cascade
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Parallel Channels for Driving Higher Current
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档　
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Layout

10.1 Layout Guidelines

To prevent thermal shutdown, the junction temperature, TJ, must be less than 150°C. If the voltage drop across the output channels is high, the device power dissipation can be large. The TLC6C5712-Q1 device has very good thermal performance because of the thermal pad design; however, the PCB layout is also very important to ensure that the device has good thermal performance. Good PCB design can optimize heat transfer, which is essential for the long-term reliability of the device.

Use the following guidelines when designing the device layout:

  • Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat-flow path from the package to the ambient is through copper on the PCB. Maximum copper density is extremely important when no heat sinks are attached to the PCB on the other side of the package.
  • Add as many thermal vias as possible directly under the package ground pad to optimize the thermal conductivity of the board.
  • Use either plated shut or plugged and capped vias for all the thermal vias on both sides of the board to prevent solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.

10.2 Layout Example

TLC6C5712-Q1 layout_ex_SLVSCO9.gif Figure 110. TLC6C7512-Q1 Layout Diagram
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