7.3.1.1 Start-Up or UVLO POR

When power is applied to V_CC, or when V_CC is undervoltage (V_CC < V_(POR)), an internal power-on reset (POR) holds the TLC6C5712-Q1 device in a reset condition with the following conditions until V_CC reaches VPOR. During RESET:

• The device cannot receive data.
• The SDO pin is held LOW, so the device cannot transmit data.
• The ERR open-drain output is pulled down.

During POR, communication between the controller and the device is lost. Any data transmitted during this period is lost. The state machine inside the device is undefined. After POR, the reset status is released, the TLC6C5712-Q1 registers and SPI state machine are re-initialized to default states (see the Default column in Table 2). [POR_ERR_FLAG] is set to HIGH during start-up or UVLO POR.

7.3.1.2 Software POR

A software reset command (<SOFTWARE_POR>) resets all internal register settings to default values. The command executes on a LATCH rising edge. All fault bits and diagnostic status are cleared and set to their default values. The <SOFTWARE_POR> command also executes the RESET_STATUS] command. The [POR_ERR_FLAG] bit in the <READ_STATUS0> register is set to HIGH on a software POR.

7.3.1.3 Reset POR

Either start-up or a UVLO POR or a software POR sets [POR_ERR_FLAG] to HIGH. when the device enters POR status, the [POR_ERR_FLAG] bit is latched HIGH. To clear the [POR_ERR_FLAG], a RESET_POR command must be issued.

If [POR_ERR_FLAG] is set either by start-up, UVLO, or software, and the device is not in any UVLO state, [POR_ERR_FLAG] is latched and does not block any operation.

7.3.1.4 POR Masking

[POR_ERR_FLAG] reporting to the ERR output can be masked by the [POR_MASK] bit. If a POR event happens when [POR_MASK] is set HIGH, POR events do not trigger the ERR̅ output, and [POR_ERR_FLAG] is set HIGH.

Figure 15. POR Error Report Topology

See the following addresses in Table 2: 61h, 62h, 63h, and A2h.

7.3.2.1 Recovery From Error

When any fault occurs, all FAULT information can be read in separate FAULT registers, for example, <READ_OPEN_FAULT0>. When the error condition recovers, the register information is still latched and the ERR pin remains low until the fault is masked or the RESET_STATUS command has been issued. However, if the error condition still exists after issuing the RESET_STATUS command, the ERR pin pulls low again and the corresponding FAULT register is set HIGH.

7.3.2.2 RESET_STATUS Command

The RESET_STATUS command clears all flags in the following registers:

<READ_ADJSHORT0>
<READ_ADJSHORT1>
<READ_SHORT_FAULT0>
<READ_SHORT_FAULT1>
<READ_SHORT_GND_FAULT0>
<READ_SHORT_GND_FAULT1>
<READ_OPEN_FAULT0>
<READ_OPEN_FAULT1>
<READ_PWM_FAULT>
<READ_STATUS0>, excluding the [POR_ERR_FLAG] bit.

As mentioned in the POR section, only the RESET_POR command can clear the [POR_ERR_FLAG] bit.

[POR_ERR_FLAG] bit: Read only (R) bit. HIGH: A POR error has occurred. To reset this flag, issue a RESET_POR command.

[POR_MASK] bit: Read and write (R/W) bit. HIGH: A POR error is stored in the [POR_ERR_FLAG] bit and is not reported to ERR.

RESET_POR: A command to reset [POR_ERR_FLAG].

SOFTWARE_POR: A command to generate a POR. It also clears STATUS flags.

See the following addresses in Table 2: 62h, 9Ah through A2h, A8h, and A9h.

7.3.3.1 PWM Dimming

PWM dimming is supported on all 12 channels by six PWM inputs. The input PWMx signal is active-low. Due to the minimal pulse duration needed for diagnostics, at 200 Hz the minimum achievable duty cycle is 0.1%, or 5 µs minimal on-time. Similarly, the maximum achievable duty cycle is 99.2%, or 40 µs minimum off-time. The setting of this boundary allows enough time for diagnostic functions. In the case of 0% or 100% PWM, diagnostics are not reported.

7.3.3.2 PWM Monitor

Independent rising-edge triggered timers are implemented as PWM monitors for each PWMx input channel. when the timer length reaches the threshold t_PWM, [PWM_FAULTx] is set to HIGH. If the corresponding masking register [PWM_FAULT_MASKx] is also set HIGH, the fault is stored in [PWM_FAULTx] and is not reported to the [ANY_PWM_FAULT_FLAG] register. [ANY_PWM_FAULT_FLAG] is set to HIGH and the ERR pin is pulled LOW if any of the PWM monitors reported a fault and the mask register [PWM_MASK] is disabled. The PWM rising edge resets the timer and restarts counting from 0. For 0% or 100% PWM, the [PWM_FAULTx] registers should be independently masked for each PWMx input via the [PWM_FAULT_MASKx] registers.

Figure 16. PWM Fault Report Topology

After being set HIGH, [PWM_FAULTx] FAULT_PWMx is latched even if the corresponding PWM input toggling has recovered. The RESET_STATUS command must be issued to clear the [ANY_PWM_FAULT_FLAG] bit.

7.3.3.3 PWM Mapping

Each of the 12 output channels has a 3-bit [PWM_MAP_CH] field to assign to one PWMx input. All output channels are assigned to PWM0 by default. Table 1 lists the mapping for each PWMx input..

7.3.3.4 PWM MAP Register Lock

To avoid unintended modification of the <PWM MAPx> registers, the <PWM MAPx> registers can be locked via the LOCK_MAP command and unlocked via the UNLOCK_MAP command. For details, see the Register Protection feature.

See the following addresses in Table 2: 40h through 45h, 60h, 62h, 66h through 68h, 6Ch, A0h through A3h, A6h, and A7h.

7.3.4.1 Global Current Reference

Maximum channel output current (dot-correction register [OUTPUT_DC_CHx] is set at full range, FFh) is globally set by reference resistor R_(IREF). The V_(IREF) voltage biases external reference resistor R_(IREF), generating reference current I_(IREF). I_(IREF) is sensed and amplified by the ratio of K_(OUT) as the maximum output current. Choose the external resistor R_(IREF) value using Equation 1, based on maximum current I_{(OUT,MAX|DC=255}.

Equation 1.

7.3.4.2 Current Reference Monitor and Protection

The TLC6C5712-Q1 device implements a current-reference monitor for current-reference resistor open-and-short diagnostic and protection. The device monitors the current I_(IREF) flowing out of the IREF pin. If I_(IREF) is higher than I_{(IREF_scth)}, a reference-short condition is asserted, limiting the I_(IREF) output current for short protection. If the I_(IREF) current is smaller than I_{I(IREF_octh)}, a reference-open condition is asserted.

To maintain output function when the IREF resistor is in a short or open condition, device switches to a fail-safe current source. In fail-safe mode, the maximum output current is defined as I_{(OUTx_default)}. when the external fault condition is removed, the external resistor sets the I_(IREF) current.

Equation 2.

To avoid switching into default current unintentionally, the device implements a digital deglitch filter on the reference open and short diagnostics. The filter length is defined as t_{(REF_deg)}. On assertion of the reference open-or-short fault, the [REF_FAULT_FLAG] bit is set. The [REF_MASK] bit can be used to mask the reference fault output to the ERR pin. If [REF_MASK] is enabled, a reference fault is not reported to the ERR output. If [REF_MASK] is enabled, a reference fault is not reported to the ERR output. Clearing the [REF_FAULT_FLAG] bit requires issuing the RESET_STATUS command.

Figure 17. Reference Fault Report Topology

7.3.4.3 Channel Activation Control

[CH_ON_MASKx] are the channel activation mask bits which control each channel output ACTIVATED-DEACTIVATED. Logic LOW stands for channel ACTIVATED status.

DEACTIVTING a channel output does not clear the diagnostics registers.

7.3.4.4 Individual Dot Correction Control

Each channel has an internal 8-bit linear-current digital-to-analog converter for individual dot correction control. The 8-bit [OUTPUT_DC_CHx] fields are used to control DAC output current according to Equation 3. Note that the minimum current is 1 / 256 of I_OUT,MAX. If absolutely zero current is required in some scenarios, the channel can be disabled by setting the corresponding channel-enable [CH_ON_MASKx] bit HIGH.

Equation 3.

7.3.4.5 Output Slew-Rate Adjustment

To accommodate different slew rate requirements for EMC optimization, the [SLOW_SLEW_RATE] bit is provided. Setting [SLOW_SLEW_RATE] HIGH makes both the rising and falling times, t_r and t_f, longer.

7.3.4.6 Register Lock

To avoid unintended modification of registers, the [OUTPUT_DC_CHx] fields can be locked with the LOCK_CORR command and unlocked with the UNLOCK_CORR command. The [CH_ON_MASKx] bits can be locked with the LOCK_MASK command and unlocked with the UNLOCK_MASK command. For details, see the Register Protection section.

7.3.4.7 Deactivated-Channel Internal Pullup

To avoid floating outputs on a deactivated channel, optional pullup current to the SENSE node I_{(OUT_PULLUP)} is provided. The pullup current is disabled by default and can be enabled by setting the [DIS_PULL_UP_CHx] bit HIGH.

See the following addresses in Table 2: 46h through 43h, 69h, 6Ah, 6Dh, 6Eh, and 86h through 93h.

7.3.5.1 Pre-Thermal Warning and Thermal Shutdown Protection

When the junction temperature exceeds the pre-thermal-warning threshold T_(PTW), [PRE_TSD_FLAG] in the <READ_STATUS0> register is set HIGH to signal the pre-thermal warning. The ERR̅ open-drain output is also pulled down. The microcontroller should respond to the fault warning and take actions to prevent junction temperature rising.

If junction temperature continues to rise and exceeds thermal-shutdown threshold T_(TSD), the overtemperature fault bit [TSD_FLAG] in the <READ_STATUS0> register is set HIGH to signal thermal shutdown, the ERR open-drain output is also pulled down, and all output channels are turned off for protection.

[PRE_TSD_FLAG] and [TSD_FLAG] are latched when triggered. To clear either of the flags, issue the RESET_STATUS command.

[TSD_FLAG] is latched after having been set. After the die temperature falls below T_(TSD) – T_(HYS), the LED outputs are activated using the previous settings without re-initializing.

The flag bits can be individually masked by [PRE_TSD_MASK] and [TSD_MASK]. [PRE_TSD_MASK] prevents the ERR̅ open-drain output. [TSD_MASK] prevents the ERR̅ open-drain output and thermal shutdown of all channels. Even if the faults are masked, the fault status can still be read in the registers.

Figure 18. Thermal Fault Report Topology

7.3.5.2 LED Short-to-Supply Detection

The device has independent LED short-to-supply detection for each channel. Whether the channel PWM source is HIGH or LOW, the voltage difference between the SENSE and OUTx pins is monitored.

If an LED short to the supply is detected, the [SHORT_FAULT_CHx] bit of the channel is set HIGH and the [ANY_SHORT_FLAG] bit is set HIGH The [ANY_SHORT_FLAG] also pulls down the ERR̅ open-drain output.

The LED short-to-supply fault does not disable the corresponding channel output. when the fault condition is removed, the LED should resume normal operation. Fault conditions are latched in the [SHORT_FAULT_CHx] bits. To clear the [SHORT_FAULT_CHx] bits, issue the RESET_STATUS command.

The [SHORT_FAULT_CHx] bits can be masked independently for each channel by the [SHORT_MASK_CHx] bits. when the [SHORT_MASK_CHx] bit of any channel is set HIGH, the short-to-supply fault on the specific channel is not reported to [ANY_SHORT_FLAG].

7.3.5.3 LED Short-to-GND Detection

The TLC6C5712-Q1 device is able to distinguish an LED short-to-GND condition from an LED open-detection condition by having an internal pullup current to the SENSE node. The pullup is enabled during the PWM OFF state or channel-deactivated state.

If an LED short-to-GND is detected, the [SG_FAULT_CHx] bit for the channel is set HIGH, and the [ANY_SHORT_FLAG] bit is also set HIGH. [ANY_SHORT_FLAG] also pulls down the ERR̅ open-drain output.

An LED short-to-GND fault does not disable the corresponding channel output. when a fault condition is removed, the LED should resume normal operation. Fault conditions are latched in the [SG_FAULT_CHx] fault bits. Issue a RESET_STATUS command to clear the [SG_FAULT_CHx] fault bits.

The [SG_FAULT_CHx] channel-fault bits can be masked independently by [SG_MASK_CHx]. when the [SG_MASK_CHx] bit of any channel is set HIGH, the short-to-GND fault on the specific channel is not reported to [ANY_SHORT_FLAG].

Figure 19. Short Fault Report Topology

7.3.5.4 LED Open-Load Detection

The device has independent LED open-load detection for each channel. If an LED open-load condition is detected, the [OPEN_FAULT_CHx] bit for the channel is set HIGH, and the [ANY_OPEN_FLAG] bit also is set HIGH. [ANY_OPEN_FLAG] also pulls down the ERR open-drain output.

An LED open-load fault does not disable the corresponding channel output. when a fault condition is removed, the LED should resume normal operation. Fault conditions are latched in the [OPEN_FAULT_CHx] fault bits. Issue a RESET_STATUS command to clear the [OPEN_FAULT_CHx] fault bits.

The [OPEN_FAULT_CHx] channel-fault bits can be masked independently by the [OPEN_MASK_CHx] bits. when the [OPEN_MASK_CHx] bit of any channel is set HIGH, the open-load fault on the specific channel is not reported to the [ANY_OPEN_FLAG] bit.

[ANY_OPEN_FLAG] is the indicator for open-load detectors. [ANY_OPEN_FLAG] can be masked by [OPEN_MASK] to avoid pulling down the ERR̅ open-drain output.

Figure 20. Open Fault Report Topology

7.3.5.5 Deactivated-Channel LED Open or Short Detection

Deactivating a channel by setting [CH_ON_MASKx] automatically enables detection of an off-state LED open load, short to the supply, or short to GND. If a fault is detected when the pullup is enabled, the respective fault register is set and the ERR̅ open-drain output is pulled down.

To clear the fault, issue the RESET_STATUS command, the same as for activated-state diagnostics. The fault-masking mechanism is also the same as for activated-state diagnostics.

If an application allows absolutely no current during the channel disabled state, disable the off-state LED open-or-short detection feature using the [DIS_OFF_FAULT_DIAG] bit.

There is a provision for pulling each channel up to SENSE to avoid a floating node during off-state. This function can be enabled by setting the [DIS_PULL_UP_CHx] bit to HIGH. If any [DIS_PULL_UP_CHx] bit is set HIGH, the [DIS_PULL_UP_FLAG] bit is also set HIGH.

7.3.5.6 Weak LED Supply (WLS) Detection

The TLC6C5712-Q1 device provides weak-LED-supply detection to avoid reporting false faults due to supply failure. Implementation of weak-LED-supply detection is by monitoring the V_(SENSE) voltage using the internal threshold voltage V_(WLS) as a reference.

The default threshold V_(WLS) is set for a 5-V supply. If a 3.3-V LED supply is needed, the threshold voltage can be tuned to V_{(WLS_OPT)} by setting the [WLS_TH] bit HIGH.

when a fault is detected, the [WLS_FAULT_FLAG] bit is set if the [WLS_MASK] masking bit is not active. The [WLS_FAULT_FLAG] bit remains latched even if the voltage recovers. To clear the fault, issue the RESET_STATUS command.

Figure 21. Weak-LED-Supply Fault-Report Topology

7.3.6.1 Dot Correction Register Lock and Unlock

The <WRITE_CORRx> dot correction register can be locked via the LOCK_CORRcommand. When it is locked, no data in the <WRITE_CORRx> registers can be altered. To unlock, issue the UNLOCK_CORR command.

7.3.6.2 PWM Mapping Register Lock and Unlock

The <WRITE_MAPx> dot correction register can be locked via the LOCK_MAP command. When it is locked, no data in the <WRITE_MAPx> registers can be altered. To unlock, issue the UNLOCK_MAP command.

7.3.6.3 Masking Register Lock and Unlock

Masking registers can be locked via LOCK_MASK command. When it is locked, no data in the masking registers listed in the Register Protection section can be altered. To unlock, issue the UNLOCK_MASK command.

7.3.6.4 Miscellaneous Register Lock and Unlock

Miscellaneous registers can be locked via the LOCK_MISC command. When it is locked, no data in the miscellaneous register listed in the Register Protection section can be altered. To unlock, issue the UNLOCK_MISC command.

7.3.6.5 Lock Flag Indication

The status of all lock registers is stored in the [LOCK_CORR_FLAG], [LOCK_MASK_FLAG], [LOCK_MAP_FLAG] and [LOCK_MISC_FLAG] bits of the <READ_STATUS1> register.

Table 3. WRITE_MAP0 Register Field Descriptions

Table 4. WRITE_MAP1 Register Field Descriptions

Table 5. WRITE_MAP2 Register Field Descriptions

Table 6. WRITE_MAP3 Register Field Descriptions

Table 7. WRITE_MAP4 Register Field Descriptions

Table 8. WRITE_MAP5 Register Field Descriptions

Table 9. WRITE_CORR0 Register Field Descriptions

Table 10. WRITE_CORR1 Register Field Descriptions

Table 11. WRITE_CORR2 Register Field Descriptions

Table 12. WRITE_CORR3 Register Field Descriptions

Table 13. WRITE_CORR4 Register Field Descriptions

Table 14. WRITE_CORR5 Register Field Descriptions

Table 15. WRITE_CORR6 Register Field Descriptions

Table 16. WRITE_CORR7 Register Field Descriptions

Table 17. WRITE_CORR8 Register Field Descriptions

Table 18. WRITE_CORR9 Register Field Descriptions

Table 19. WRITE_CORR10 Register Field Descriptions

Table 20. WRITE_CORR11 Register Field Descriptions

Table 21. WRITE_CH_ON_MASK0 Field Descriptions

Table 22. WRITE_CH_ON_MASK1 Field Descriptions

Table 23. WRITE_SHORT_MASK0 Field Descriptions

Table 24. WRITE_SHORT_MASK1 Field Descriptions

Table 25. WRITE_SHORT_GND_MASK0 Field Descriptions

Table 26. WRITE_SHORT_GND_MASK1 Field Descriptions

Table 27. WRITE_OPEN_MASK0 Field Descriptions

Table 28. WRITE_OPEN_MASK1 Field Descriptions

Table 29. WRITE_PWM_FAULT_MASK Field Descriptions

Table 30. RESET_POR Field Descriptions

Table 31. RESET_STATUS Field Descriptions

Table 32. SOFTWARE_POR Field Descriptions

Table 33. WRITE_DIS_PULL_UP_0 Field Descriptions

Table 34. WRITE_DIS_PULL_UP_1 Field Descriptions

Table 35. WRITE_ERROR_MASK Field Descriptions

Table 36. WRITE_MISC_CMD Field Descriptions

Table 37. LOCK_MAP Field Descriptions

Table 38. LOCK_CORR Field Descriptions

Table 39. LOCK_MASK Field Descriptions

Table 40. LOCK_MISC Field Descriptions

Table 41. UNLOCK_MAP Field Descriptions

Table 42. UNLOCK_CORR Field Descriptions

Table 43. UNLOCK_MASK Field Descriptions

Table 44. UNLOCK_MISC Field Descriptions

Table 45. READ_SHORT_FAULT0 Register Field Descriptions

Table 46. READ_SHORT_FAULT1 Register Field Descriptions

Table 47. READ_SHORT_GND_FAULT0 Register Field Descriptions

Table 48. READ_SHORT_GND_FAULT1 Register Field Descriptions

Table 49. READ_OPEN_FAULT0 Register Field Descriptions

Table 50. READ_OPEN_FAULT1 Register Field Descriptions

Table 51. READ_STATUS0 Register Field Descriptions

Table 52. READ_STATUS1 Register Field Descriptions

Table 53. READ_ADSHORT0 Register Field Descriptions

Table 54. READ_ADSHORT1 Register Field Descriptions