7.5.1.2 Grayscale Data Write

The grayscale data is 288 bits long, and contains a 12-bit grayscale value for each output. The grayscale value sets the channel turnon time.Figure 27 shows the GS register configuration. Figure 1 is the GS write timing diagram. Data is latched from the 288-bit common shift register into the GS data latch at the rising edge of the LATCH pin. When data is latched into the GS registers, the new data is immediately available on the constant-current outputs. If the data is latched with BLANK high, the outputs may turn on or off unexpectedly. So users should update the GS data when BLANK is low.

The 12-bit GS function has 4096 brightness steps, from 0% to 99.97% brightness. The GS function is controlled by a 12-bit GS counter. The GS counter increments on each rising edge of the grayscale reference clock GCLK. The falling edge of BLANK resets the GS counter value to 0. The GS counter value stays at 0 while BLANK is low, even if there is a GCLK input. Pulling BLANK high enables the 12-bit GS counter. The first rising edge of a GS clock after BLANK goes high increments the GS counter by one and turns on the outputs. Each additional rising edge increases the GS counter by one. The GS counter monitors the number of clock pulses on the GCLK pin. The output stays on while the counter value is less than or equal to the GS setting value. The output turns off at the rising edge of the GS counter value when the counter is larger than the GS setting value. Table 20 is the on-time duty cycle of each GS data bit when the 12-bit GS counter mode is selected.

When the device is powered up, the 288-bit common shift register and GS data latch are reset to 0.

Equation 4 describes each output on-time.

Equation 4.

where

• t_GCLK is the GS clock period
• GS is the programmed grayscale value for each output.

Equation 5 shows the duty-cycle calculation equation.

Equation 5.

Figure 27. TLC6C5716-Q1 Grayscale Register

Once the GS data is latched into the GS registers at the rising edge of the LATCH signal, the FC-BC-DC data latch shifts into the lowest 205 bits of the common shift register. So, the FC-BC-DC data can be read out from SDO in GS write. This FC-BC-DC read function can also be realized by the read FC-BC-DC command, see FC-BC-DC Read and Figure 8 for the timing diagram.