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ZHCSIO0A December 2017 – August 2018 TLC6C5724-Q1

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- MPDS381

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7.3.4.1 LED Diagnostics

An LOD-LSD detection circuit compares the output voltage with the LOD threshold and LSD threshold, and the output results show in Table 1.

Table 1. LOD-LSD Detection

OUTPUT VOLTAGE CONDITION	DETECTOR OUTPUT BIT VALUE
OUTPUT VOLTAGE CONDITION	LOD	LSD
V_OUTn < LOD_VOLTAGE	1	0
LOD_VOLTAGE < V_OUTn < LSD_VOLTAGE	0	0
V_OUTn > LSD_VOLTAGE	0	1

The LOD threshold can be configured by the LOD_VOLTAGE bit. The threshold is 0.3 V when LOD_VOLTAGE = 0, and the threshold is 0.5 V when LOD_VOLTAGE = 1.

Table 2. LOD Threshold

LOD_VOLTAGE BIT	LOD THRESHOLD
0 (Default)	0.3 V
1	0.5 V

LSD threshold is configured by the LSD_VOLTAGE bit. The threshold is V_VSENSE – 0.3 V when LSD_VOLTAGE = 0, and the threshold is VSENSE – 0.7 V when LSD_VOLTAGE = 1.

Table 3. LSD Threshold

LSD_VOLTAGE BIT	LSD THRESHOLD
0 (Default)	V_SENSE– 0.3 V
1	V_SENSE – 0.7 V

There are two sets of LOD-LSD registers in the device. One is the LOD1-LSD1 registers, another is the LOD2-LSD2 registers. Each group of registers consists of 24 bits of LOD data and 24 bits of LSD data, corresponding to 24 channel outputs. The device updates the LOD1-LSD1 registers at the 9th GCLK rising edge. The device updates the LOD2-LSD2 registers the Nth GCLK rising edge. N is the maximum GCLK number in a PWM period minus 1, see Table 4.

To detect all kinds of LED faults, the output channel should turn ON at the 9th GCLK rising edge, and turn OFF at the Nth GCLK rising edge.

The device integrates an internal pullup circuit for LED diagnostics, shown in Figure 23. The circuit turns off during the channel on-state, but turns on to charge the output pin during the channel off-state. For an LED-short fault, both LSD1 and LSD2 are 1. For an LED-open fault, both LOD1 and LSD2 are 1. For an output short-to-GND fault, both LOD1 and LOD2 are 1. Table 5 shows the details.

Figure 23. Internal Pullup Circuit

Table 4. LOD-LSD Register Latch Timing

GS COUNTER MODE	LOD1-LSD1	LOD2-LSD2
12-bit	9th GCLK rising edge	4095th GCLK rising edge
10-bit	9th GCLK rising edge	1023rd GCLK rising edge
8-bit	9th GCLK rising edge	255th GCLK rising edge

Table 5. LED Status Lookup Table

LED STATUS	LOD-LSD RESULT
LED STATUS	LOD1-LSD1 UPDATED AT 9^th GCLK		LOD2-LSD2 UPDATED AT N^th GCLK⁽¹⁾
LED Ok	LOD1	0	LOD2	0
LED Ok	LSD1	0	LSD2	1
LED open	LOD1	1	LOD2	0
LED open	LSD1	0	LSD2	1
LED short	LOD1	0	LOD2	0
LED short	LSD1	1	LSD2	1
Output short-to-GND	LOD1	1	LOD2	1
Output short-to-GND	LSD1	0	LSD2	0

(1) N = 4095 for 12-bit GS mode, 1023 for 10-bit GS mode, 255 for 8-bit GS mode

In some cases, users may need to turn off output channels before the 9th GCLK to disable output channels, or turn on output channels at Nth GCLK to get more brightness. LOD_LSD faults are reported as shown in Table 6. Users can ignore the fault according to the GS register setting value.

Table 6. PWM Status Lookup Table

	LOD-LSD RESULT
PWM STATUS	LOD1-LSD1 UPDATED AT 9^th GCLK		LOD2-LSD2 UPDATED AT N^th GCLK⁽¹⁾
PWM OK	LOD1	0	LOD2	0
PWM OK	LSD1	0	LSD2	1
Channel off before 9th GCLK	LOD1	0	LOD2	0
Channel off before 9th GCLK	LSD1	1	LSD2	1
Channel on at Nth GCLK	LOD1	0	LOD2	0
Channel on at Nth GCLK	LSD1	0	LSD2	0

(1) N = 4095 for the 12-bit GS mode, 1023 for the 10-bit GS mode, 255 for the 8-bit GS mode

The LOD_LSD status is updated every PWM cycle. Figure 14 is an example of the LOD-LSD register update timing for the 12-bit GS mode.