Figure 11 and Figure 12 show the resistive-load test circuit and voltage waveforms. One can see from Figure 12 that with G held low and CLR held high, the status of each drain changes on the rising edge of the register clock, indicating the transfer of data to the output buffers at that time.

A. C_L includes probe and jig capacitance.

Figure 11. Resistive-Load Test Circuit

Figure 12. Voltage Waveforms