SLIS142D December 2012 – September 2016 TLC6C598-Q1
PRODUCTION DATA.
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| CLR | 7 | I | Shift register clear, active-low. The storage register transfers data to the output buffer when CLR is high. Driving CLR low clears all the registers in the device. |
| DRAIN0 | 3 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
| DRAIN1 | 4 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
| DRAIN2 | 5 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
| DRAIN3 | 6 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
| DRAIN4 | 11 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
| DRAIN5 | 12 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
| DRAIN6 | 13 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
| DRAIN7 | 14 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
| G | 8 | I | Output enable, active-low. LED-channel enable and disable input pin. Having G low enables all drain channels according to the output-latch register content. When high, all channels are off. |
| GND | 16 | — | Power ground, the ground reference pin for the device. This pin must connect to the ground plane on the PCB. |
| RCK | 10 | I | Register clock. The data in each shift register stage transfers to the storage register at the rising edge of RCK. |
| SER IN | 2 | I | Serial data input. Data on SER IN loads into the internal register on each rising edge of SRCK. |
| SER OUT | 9 | O | Serial data output of the 8-bit serial shift register. The purpose of this pin is to cascade several devices on the serial bus. |
| SRCK | 15 | I | Serial clock input. On each rising SRCK edge, data transfers from SER IN to the internal serial shift registers. |
| VCC | 1 | I | Power supply pin for the device. TI recommends adding a 0.1-μF ceramic capacitor close to the pin. |