米6体育平台手机版

ZHCSMY5B December 2020 – April 2022 TLIN1021A-Q1

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

D|8
- MSOI002K
DRB|8
- MPDS118K
DDF|8
- MPDS569D

散热焊盘机械数据 (封装 | 引脚)

DRB|8
- QFND619

订购信息

7.7 Electrical Characteristics

parameters valid across -40℃ ≤ T_J ≤ 150℃ (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
RXD Output Terminal
V_OL	Low-level voltage	Based upon external pull-up to V_CC⁽⁴⁾			0.6	V
I_OL	Low-level output current, open drain	LIN = 0 V, RXD = 0.4 V	1.5			mA
I_LKG	Leakage current, high-level	LIN = V_SUP, RXD = V_CC	–5		5	µA
TXD Input Terminal
V_IL	Low-level input voltage				0.8	V
V_IH	High-level input voltage		2			V
I_LKG	Low-level input leakage current	TXD = 0 V	–5		5	µA
I_TXD(WAKE)	Local wake-up source recognition TXD	Standby mode after a local wake-up event V_LIN = V_SUP, WAKE = 0 V or V_SUP, TXD = 1 V	1.3		8	mA
R_TXD	Internal pull-down resistor value		125	350	800	kΩ
EN Input Terminal
V_IL	Low-level input voltage		–0.3		0.8	V
V_IH	High-level input voltage		2		5.25	V
V_HYS	Hysteresis voltage	By design and characterization	30		500	mV
I_IL	Low-level input current	EN = 0 V	–5		5	µA
R_EN	Internal pull-down resistor		125	350	800	kΩ
LIN Terminal (Referenced to V_SUP)
V_OH	LIN recessive high-level output voltage⁽³⁾	TXD = V_CC, I_O = 0 mA 7 V ≤ V_SUP ≤ 36 V	0.85			V_SUP
V_OH	LIN recessive high-level output voltage⁽¹⁾⁽²⁾	TXD = V_CC, I_O = 0 mA 7 V ≤ V_SUP ≤ 18 V	0.8			V_SUP
V_OH	LIN recessive high-level output voltage⁽³⁾	TXD = V_CC, I_O = 0 mA 4.5 V ≤ V_SUP ≤ 7 V	3			V
V_OL	LIN dominant low-level output voltage⁽³⁾	TXD = 0 V 7 V ≤ V_SUP ≤ 36 V			0.2	V_SUP
V_OL	LIN dominant low-level output voltage⁽¹⁾⁽²⁾	TXD = 0 V 7 V ≤ V_SUP ≤ 18 V			0.2	V_SUP
V_OL	LIN dominant low-level output voltage⁽³⁾	TXD = 0 V 4.5 V ≤ V_SUP ≤ 7 V			1.2	V
V_BUSdom	Low-level input voltage⁽³⁾	LIN dominant (including LIN dominant for wake up) See Figure 8-3 See Figure 8-4			0.4	V_SUP
V_BUSrec	High-level input voltage⁽³⁾	Lin recessive See Figure 8-3 See Figure 8-4	0.6			V_SUP
V_IH	LIN recessive high-level input voltage⁽¹⁾⁽²⁾	7 V ≤ V_SUP ≤ 18 V	0.47		0.6	V_SUP
V_IL	LIN dominant low-level input voltge⁽¹⁾⁽²⁾	7 V ≤ V_SUP ≤ 18 V	0.4		0.53	V_SUP
V_{SUP_NON_OP}	V_SUP where impact of recessive LIN bus < 5%⁽³⁾	TXD & RXD open 4.5 V ≤ V_LIN ≤ 45 V	–0.3		42	V
V_{BUS_CNT}	Receiver center threshold⁽³⁾	V_{BUS_CNT} = (V_BUSrec + V_BUSdom)/2 See Figure 8-3 See Figure 8-4	0.475	0.5	0.525	V_SUP
V_HYS	Hysteresis voltage (ISO 17987)	V_HYS = V_BUSrec - V_BUSdom See Figure 8-3 See Figure 8-4			0.175	V_SUP
V_HYS	Hysteresis voltage (SAE J2602)	V_HYS = V_IH - V_IL See Figure 8-3 See Figure 8-4	0.07		0.175	V_SUP
V_{SERIAL_DIODE}	Serial diode LIN termination pull-up path	I_{SERIAL_DIODE} = 10 µA	0.4	0.7	1.0	V
I_BUS(LIM)	Limiting current ISO 17987 Param 12	TXD = 0 V, V_LIN = 18 V, V_SUP = 18 V	40	90	200	mA
I_{BUS_PAS_dom}	Receiver leakage current, dominant	Driver off/recessive, LIN = 0 V V_SUP = 12 V See Figure 8-6	–1			mA
I_{BUS_PAS_rec1}	Receiver leakage current, recessive	Driver off/recessive, LIN ≥ V_SUP 4.5 V ≤ V_SUP ≤ 36 V See Figure 8-7			20	µA
I_{BUS_PAS_rec2}	Receiver leakage current, recessive	Driver off/recessive, LIN = V_SUP See Figure 8-7	–5		5	µA
I_{BUS_NO_GND}	Leakage current, loss of ground	GND_Device = V_SUP = 18 V R_Meas = 1 kΩ 0 V < V_LIN< 18 V	–1		1	mA
I_{leak gnd(dom)}	Leakage current, loss of ground⁽⁵⁾	V_SUP = 8 V, GND = open, V_SUP = 18 V, GND = open R_Commander = 1 kΩ, C_L = 1 nF R_Responder = 20 kΩ, C_L = 1 nF LIN = dominant	–1		1	mA
I_{leak gnd(rec)}	Leakage current, loss of ground⁽⁵⁾	V_SUP = 8 V, GND = open, V_SUP = 18 V, GND = open R_Commander = 1 kΩ, C_L = 1 nF R_Responder = 20 kΩ, C_L = 1 nF LIN = recessive	–100		100	µA
I_{BUS_NO_BAT}	Leakage current, loss of supply	V_SUP = GND 0 V ≤ V_LIN≤ 18 V			5	µA
I_RSLEEP	Pull-up current source to V_SUP sleep mode	V_SUP = 14 V, LIN = GND	–20		–1.5	µA
R_PU	Internal pull-up resistor to V_SUP	Normal and standby modes	20	45	60	kΩ
C_LIN	Capacitance of the LIN pin	V_SUP = 14 V			25	pF
INH Output Terminal
ΔV_H	High level voltage drop INH with respect to V_SUP	I_INH = - 0.5 mA		0.5	1	V
I_LKG(INH)	Leakage current sleep mode	INH = 0 V	–0.5		0.5	µA
WAKE Input Terminal
V_IH	High-level input voltage	Standby and sleep mode	V_SUP – 1.8			V
V_IL	Low-level input voltage	Standby and sleep mode			V_SUP – 3.85	V
I_IH	High-level input leakage current	WAKE = V_SUP - 1 V	–25	–12.5		µA
I_IL	Low-level input leakage current	WAKE = 1 V		15	25	µA
t_WAKE	WAKE hold time	Wake up time from sleep mode	5		50	µs
Duty Cycle Characteristics
D1	Duty cycle 1⁽³⁾ ISO 17987 Param 27	TH_REC(MAX) = 0.744 x V_SUP, TH_DOM(MAX) = 0.581 x V_SUP, V_SUP = 7 V to 18 V, t_BIT = 50 µs D1 = t_{BUS_rec(min)}/(2 x t_BIT) See Figure 8-8 and Figure 8-9	0.396
D1	Duty cycle 1⁽³⁾⁽⁶⁾	TH_REC(MAX) = 0.665 x V_SUP, TH_DOM(MAX) = 0.499 x V_SUP V_SUP = 4.5 V to 7 V, t_BIT = 50 µs D1 = t_{BUS_rec(min)}/(2 x t_BIT) See Figure 8-8 and Figure 8-9	0.396
D1	Duty cycle 1⁽¹⁾⁽²⁾⁽⁶⁾	TH_REC(MAX) = 0.744 x V_SUP, TH_DOM(MAX) = 0.581 x V_SUP, V_SUP = 7 V to 18 V, t_BIT = 52 µs D1 = t_{BUS_rec(min)}/(2 x t_BIT) See Figure 8-8 and Figure 8-9	0.396
D2	Duty cycle 2⁽³⁾ ISO 17987 Param 28	TH_REC(MIN) = 0.422 x V_SUP, TH_DOM(MIN) = 0.284 x V_SUP, V_SUP = 7 V to 18 V, t_BIT = 50 µs D2 = t_{BUS_rec(MAX)}/(2 x t_BIT) See Figure 8-8 and Figure 8-9			0.581
D2	Duty cycle 2⁽³⁾⁽⁶⁾	TH_REC(MIN) = 0.496 x V_SUP, TH_DOM(MIN) = 0.361 x V_SUP, V_SUP = 4.5 V to 7 V, t_BIT = 50 µs D2 = t_{BUS_rec(MAX)}/(2 x t_BIT) See Figure 8-8 and Figure 8-9			0.581
D2	Duty cycle 2⁽¹⁾⁽²⁾⁽⁶⁾	TH_REC(MIN) = 0.422 x V_SUP, TH_DOM(MIN) = 0.284 x V_SUP, V_SUP = 7 V to 18 V, t_BIT = 52 µs D2 = t_{BUS_rec(MAX)}/(2 x t_BIT) See Figure 8-8 and Figure 8-9			0.581
D3	Duty cycle 3⁽³⁾ ISO 17987 Param 29	TH_REC(MAX) = 0.778 x V_SUP TH_DOM(MAX) = 0.616 x V_SUP V_SUP= 7 V to 18 V, t_BIT = 96 µs D3 = t_{BUS_rec(min)}/(2 x t_BIT) See Figure 8-8 and Figure 8-9	0.417
D3	Duty cycle 3⁽³⁾⁽⁶⁾	TH_REC(MAX) = 0.665 x V_SUP TH_DOM(MAX) = 0.499 x V_SUP V_SUP= 4.5 V to 7 V, t_BIT = 96 µs D3 = t_{BUS_rec(min)}/(2 x t_BIT) See Figure 8-8 and Figure 8-9	0.417
D3	Duty cycle 3⁽¹⁾⁽²⁾⁽⁶⁾	TH_REC(MAX) = 0.778 x V_SUP TH_DOM(MAX) = 0.616 x V_SUP V_SUP= 7 V to 18 V, t_BIT = 96 µs D3 = t_{BUS_rec(min)}/(2 x t_BIT) See Figure 8-8 and Figure 8-9	0.417
D4	Duty cycle 4⁽³⁾ ISO 17987 Param 30	TH_REC(MIN) = 0.389 x V_SUP TH_DOM(MIN) = 0.251 x V_SUP V_SUP= 7 V to 18 V, t_BIT = 96 µs D4 = t_{BUS_rec(MAX)}/(2 x t_BIT) See Figure 8-8 and Figure 8-9			0.59
D4	Duty cycle 4⁽³⁾⁽⁶⁾	TH_REC(MAX) = 0.496 x V_SUP TH_DOM(MAX) = 0.361 x V_SUP V_SUP= 4.5 V to 7 V, t_BIT = 96 µs D4 = t_{BUS_rec(MAX)}/(2 x t_BIT) See Figure 8-8 and Figure 8-9			0.59
D4	Duty cycle 4⁽¹⁾⁽²⁾⁽⁶⁾	TH_REC(MIN) = 0.389 x V_SUP TH_DOM(MIN) = 0.251 x V_SUP V_SUP= 7 V to 18 V, t_BIT = 96 µs D4 = t_{BUS_rec(MAX)}/(2 x t_BIT) See Figure 8-8 and Figure 8-9			0.59
D1_LB	Duty cycle 1 at low battery⁽¹⁾⁽²⁾⁽⁶⁾	TH_REC(MAX) = 0.665 x V_SUP, TH_DOM(MAX) = 0.499 x V_SUP, V_SUP = 5.5 V to 7 V, t_BIT = 52 µs	0.396
D2_LB	Duty cycle 2 at low battery⁽¹⁾⁽²⁾⁽⁶⁾	TH_REC(MAX) = 0.496 x V_SUP TH_DOM(MAX) = 0.361 x V_SUP V_SUP = 6.1 V to 7 V, t_BIT = 52 µs			0.581
D3_LB	Duty cycle 3 at low battery⁽¹⁾⁽²⁾⁽⁶⁾	TH_REC(MAX) = 0.665 x V_SUP, TH_DOM(MAX) = 0.499 x V_SUP, V_SUP = 5.5 V to 7 V, t_BIT = 96 µs	0.396
D_4LB	Duty cycle 4 at low battery⁽¹⁾⁽²⁾⁽⁶⁾	TH_REC(MAX) = 0.496 x V_SUP TH_DOM(MAX) = 0.361 x V_SUP V_SUP = 6.1 V to 7 V, t_BIT = 96 µs			0.581
T_{r-d max}	Transmitter propagation delay timings for the duty cycle⁽¹⁾⁽²⁾⁽⁶⁾ Recessive to dominant	TH_REC(MAX) = 0.744 x V_SUP, TH_DOM(MAX) = 0.581 x V_SUP 7 V ≤ V_SUP ≤ 18 V, t_BIT = 52 µs t_{REC(MAX)_D1} - t_{DOM(MIN)_D1}			10.8	µs
T_{d-r max}	Transmitter propagation delay timings for the duty cycle⁽¹⁾⁽²⁾⁽⁶⁾ Dominant to recessive	TH_REC(MAX) = 0.422 x V_SUP, TH_DOM(MAX) = 0.284 x V_SUP 7 V ≤ V_SUP ≤ 18 V, t_BIT = 52 µs t_{DOM(MAX)_D2} - t_{REC(MIN)_D2}			8.4	µs
T_{r-d max}	Transmitter propagation delay timings for the duty cycle⁽¹⁾⁽²⁾⁽⁶⁾ Recessive to dominant	TH_REC(MAX) = 0.778 x V_SUP TH_DOM(MAX) = 0.616 x V_SUP 7 V ≤ V_SUP ≤ 18 V, t_BIT = 96 µs t_{REC(MAX)_D3} - t_{DOM(MIN)_D3}			15.9	µs
T_{d-r max}	Transmitter propagation delay timings for the duty cycle⁽¹⁾⁽²⁾⁽⁶⁾ Dominant to recessive	TH_REC(MIN) = 0.389 x V_SUP TH_DOM(MIN) = 0.251 x V_SUP 7 V ≤ V_SUP ≤ 18 V, t_BIT = 96 µs t_{DOM(MAX)_D4} - t_{REC(MIN)_D4}			17.28	µs
T_{r-d max_low}	Low battery transmitter propagation delay timings for the duty cycle⁽¹⁾⁽²⁾⁽⁶⁾ Recessive to dominant	TH_REC(MAX) = 0.665 x V_SUP, TH_DOM(MAX) = 0.499 x V_SUP 5.5 V ≤ V_SUP ≤ 7 V, t_BIT = 52 µs t_{REC(MAX)_low} - t_{DOM(MIN)_low}			10.8	µs
T_{d-r max_low}	Low battery transmitter propagation delay timings for the duty cycle⁽¹⁾⁽²⁾⁽⁶⁾ Dominant to recessive	TH_REC(MAX) = 0.496 x V_SUP TH_DOM(MAX) = 0.361 x V_SUP 6.1 V ≤ V_SUP ≤ 7 V, t_BIT = 52 µs t_{DOM(MAX)_low} - t_{REC(MIN)_low}			8.4	µs

(1) SAE 2602 commander node load conditions: 5.5 nF/4 kΩ and 899 pF/20 kΩ

(2) SAE 2602 responder node load conditions: 5.5 nF/875 Ω and 899 pF/900 Ω

(3) ISO 17987 bus load conditions (C_LINBUS, R_LINBUS) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω.

(4) RXD uses open drain output structure therefore V_OL level is based upon microcontroller supply voltage.

(5) I_{leak gnd} = (V_BAT - V_LIN)/R_Load

(6) Specified by design