ZHCSOR2 August 2021 TLIN1039-Q1
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 说明（续）
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 LIN (Local Interconnect Network) Bus
- 9.3.2 TXD (Transmit Input and Output)
- 9.3.3 RXD (Receive Output)
- 9.3.4 VSUP (Supply Voltage)
- 9.3.5 GND (Ground)
- 9.3.6 EN (Enable Input)
- 9.3.7 Protection Features
- 9.3.8 TXD Dominant Timeout (DTO)
- 9.3.9 Bus Stuck Dominant System Fault: False Wake-Up Lockout
- 9.3.10 Thermal Shutdown
- 9.3.11 Under Voltage on VSUP
- 9.3.12 Unpowered Transceiver
- 9.4 Functional Modes
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
10.2.3 Application Curves
Figure 10-2 and Figure 10-3 show the propagation delay from the TXD pin to the LIN pin for the dominant to recessive and recessive to dominant edges. The device was configured as a commander node with an external pull-up resistor (1 kΩ) and 680 pF bus capacitance.
Figure 10-2 Dominant to Recessive Propagation Delay
Figure 10-3 Recessive to Dominant Propagation Delay