ZHCSNE4
June 2022
TLIN2024A-Q1
PRODUCTION DATA
1
特性
2
应用
3
说明
4
Revision History
5
说明(续)
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
ESD Ratings - IEC
7.4
Thermal Information
7.5
Recommended Operating Conditions
7.6
Electrical Characteristics
7.7
Duty Cycle Characteristics
7.8
Switching Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
LIN (Local Interconnect Network) Bus
9.3.1.1
LIN Transmitter Characteristics
9.3.1.2
LIN Receiver Characteristics
9.3.1.2.1
Termination
9.3.2
TXD (Transmit Input and Output)
9.3.3
RXD (Receive Output)
9.3.4
VSUP1/2 (Supply Voltage)
9.3.5
GND1/2 (Ground)
9.3.6
EN (Enable Input)
9.3.7
Protection Features
9.3.8
TXD Dominant Time Out (DTO)
9.3.9
Bus Stuck Dominant System Fault: False Wake-Up Lockout
9.3.10
Thermal Shutdown
9.3.11
Under Voltage on VSUP
9.3.12
Unpowered Device and LIN Bus
9.4
Device Functional Modes
9.4.1
Normal Mode
9.4.2
Sleep Mode
9.4.3
Standby Mode
9.4.4
Wake-Up Events
9.4.4.1
Wake-Up Request (RXD)
9.4.4.2
Mode Transitions
10
Application and Implementation Disclaimer
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.1.1
Detailed Design Procedures
10.2.1.2
Normal Mode Application Note
10.2.1.3
Standby Mode Application Note
10.2.1.4
TXD Dominant State Timeout Application Note
10.2.2
Application Curves
10.3
Power Supply Recommendations
10.4
Layout
10.4.1
Layout Guidelines
10.4.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
接收文档更新通知
11.3
支持资源
11.4
Trademarks
11.5
术语表
12
Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
RGY|24
MPQF143E
散热焊盘机械数据 (封装 | 引脚)
RGY|24
QFND668
订购信息
zhcsne4_oa
8
Parameter Measurement Information
Figure 8-1
Test System: Operating Voltage Range with RX and TX Access
Figure 8-2
RX Response: Operating Voltage Range
Figure 8-3
LIN Bus Input Signal
Figure 8-4
LIN Receiver Test with RX Access
Figure 8-5
V
SUP_NON_OP
Figure 8-6
Test Circuit for I
BUS_PAS_dom
; TXD = Recessive State V
BUS
= 0 V
Figure 8-7
Test Circuit for I
BUS_PAS_rec
Figure 8-8
Test Circuit for I
BUS_NO_GND
Loss of GND
Figure 8-9
Test Circuit for I
BUS_NO_BAT
Loss of Battery
Figure 8-10
Test Circuit Slope Control and Duty Cycle
Figure 8-11
Definition of Bus Timing Parameters
Figure 8-12
Propagation Delay Test Circuit
Figure 8-13
Propagation Delay
Figure 8-14
Mode Transitions
Figure 8-15
Wake-Up Through EN
Figure 8-16
Wake-Up Through LIN
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