10.1.1.1 Layout Recommendations for High-Speed Signals

Both “low-speed” side and “high-speed” side serial signals are referred to as “high-speed” signals for the purpose of this document as they support high data rates. For that reason, care must be taken to realize them on a printed circuit board with signal integrity. The high-speed data path CML input pins INA[3:0]P/INA[3:0]N and HSRXAP/HSRXAN, and the CML output pins OUTA[3:0]P/OUTA[3:0]N and HSTXAP/HSTXAN, have to be connected with loosely-coupled 100-Ω differential transmission lines. Differential intra-pair skew needs to be minimized to within ±1 mil. Inter-pair (lane-to-lane) skew for the low-speed signals can be as high as 30 UI. An example of FR-4 printed circuit board (PCB) realization of such differential transmission lines in microstrip format is shown in Figure 10-1.

Figure 10-1 Differential Microstrip PCB Trace Geometry Example

To avoid impedance discontinuities the high-speed serial signals should be routed on a PCB on either the top or bottom PCB layers in microstrip format with no vias. If vias are unavoidable, an absolute minimum number of vias need to be used. The vias should be made to stretch through the entire PCB thickness (as shown in Figure 10-2) to connect microstrip traces on the top and bottom layers of the PCB so as to leave no via stubs that can severely impact the performance. If stripline traces are absolutely necessary, and if via back-drilling is not possible, then the routing layers should be chosen so as to have via stubs that are shorter than 10 mils.

All unused internal layer via pads on high-speed signal vias should be removed to further improve impedance matching. On the high-speed side, the HSRXAP/HSRXAN signals are more sensitive to impedance discontinuities introduced by vias than HSTXAP/HSTXAN signals. For that reason, if only some of those signals need to be routed with vias, then the latter should be routed with vias and the former with no vias.

Figure 10-2 Examples of High-speed PCB Traces With Vias That Have no Via Stubs and no Via Pads on Internal Layers

To further improve on impedance matching, differential vias with neighboring ground vias can be used as shown in Figure 10-3. The optimum dimensions of such a differential via structure depend on various parameters such as the trace geometry, dielectric material, as well as the PCB layer stack-up. A 3D electromagnetic field solver can be used to find the optimum via dimensions.

Figure 10-3 A Differential PCB Via Structure (Top View)

PCB traces connected to the HSRXAP/HSRXAN pins should have differential insertion loss of less than 25 dB at 5 GHz.

Surface-mount connector pads such as those used with the SFP/SFP+ module connectors are wider and hence have characteristic impedance that is lower than the regular high-speed PCB traces. If the pads are more than 2 times wider than the PCB traces, the pads’ impedance needs to be increased to minimize impedance discontinuities. The easy way of increasing the pads’ impedance is to cut out the reference plane immediately under those pads as shown in Figure 10-4 so as to have the pads refer to a reference plane on lower layers while maintaining 100 Ω differential characteristic impedance.

Figure 10-4 Surface-mount Connector Pads

10.1.1.2 AC-coupling

A 0.1-uF series AC-coupling capacitor should be connected to each of the high-speed data path pins INA[3:0]P/INA[3:0]N, HSRXAP/HSRXAN, OUTA[3:0]P/OUTA[3:0]N, and HSTXAP/HSTXAN. If the TLK10031 high-speed side data path pins are connected to SFP/SFP+ optical modules with internal AC-coupling capacitors, then no external capacitors should be used. Adding additional series capacitors may severely impact the performance.

To avoid impedance discontinuities, it is strongly recommended where possible to make the transmission line trace width closely match the AC-coupling capacitor pad size. Smaller capacitor packages such as 0201 make it easy to meet that condition.

10.1.2.1 General Information

The TLK10031 device requires a low-jitter reference clock to work. The reference clock can be provided on the REFCLK0P/N or REFCLK1P/N pins. Both reference clock input pins have internal 100-Ω differential terminations, so they do not need any external terminations. Both reference clock inputs must be AC-coupled with preferably 0.1-µF capacitors. The two channels (A and B) can have same or different reference clocks.

10.1.2.2 External Clock Connections

An external clock jitter cleaner, such as Texas Instruments CDCE72010 or CDCM7005, may be used when needed to provide a low jitter reference clock. An example external clock jitter cleaner connection for channel A is shown in Figure 10-5.

Figure 10-5 An External Clock Jitter Cleaner Connection Example for Channel A

10.1.2.3 TLK10031 Control Pins and Interfaces

The TLK10031 device features a number of control pins and interfaces, some of which are described as follows.