Bootstrap Configuration Power Supply Configuration IO Pins Hi-Z State During Reset Auto-Negotiation Auto-MDIX MII Isolate mode

PHY Address LED Interface Loopback Functionality BIST Cable Diagnostics

Table 5-1 Strap Options

PIN		TYPE
NAME	NO.		DESCRIPTION
PHYAD0 (COL) PHYAD1 (RXD_0) PHYAD2 (RXD_1) PHYAD3 (RXD_2) PHYAD4 (RXD_3)	29 30 31 32 1	S, O, PD / PU	PHY Address [4:0]: The TLK10xL provides five PHY address pins, the states of which are latched into an internal register at system hardware reset. The TLK10xL supports PHY Address values 0 (<00000>) through 31 (<11111>). PHYAD[4:1] pins have weak internal pull-down resistors, and PHYAD[0] has weak internal pull-up resistor, setting the default PHYAD if no external resistors are connected.
AN_0 (LED_LINK)	17	S, O, PU	AN_0: FD-HD config. FD = pull up. The default wake-up is auto negotiation enable 100BT.
LED_CFG (CRS)	27	S, O, PU	LED Configuration: This option selects the operation mode of the LED LINK pin. Default is Mode 1. All modes are also configurable via register access. See PHY Control Register (PHYCR), Address 0x0019.
AMDIX_EN (RX_ER)	28	S, O, PU	Auto-MDIX Enable: This option sets the Auto-MDIX mode. By default, it enables Auto-MDIX. An external pull-down resistor disables Auto-MDIX mode.
MII_MODE (RX_DV)	26	S, O, PD	MII Mode Select: This option selects the operating mode of the MAC data interface. This pin has a weak internal pull-down, and it defaults to normal MII operation mode. An external pull-up causes the device to operate in RMII mode.

5.1.2.1 Single Supply Operation

If a single 3.3V power supply is desired, the TLK10xL internal regulator provides the necessary core supply voltages. Ceramic capacitors of 10µf and 0.1µf should be placed close to the PFBOUT (pin 15) which is the output of the internal regulator. The PFBOUT pin should be connected to the PFBIN1 and PFBIN2 on the board. A small capacitor of 0.1µF should be placed close to the PFBIN1 (pin 13) and PFBIN2 (pin 24). To operate in this mode, connect the TLK10xL supply pins as shown in Figure 5-1.

5.1.2.2 Dual Supply Operation

When a 1.55V external power rail is available, the TLK10xL can be configured as shown in Figure 5-2. PFBOUT (pin 15) is left floating. The 1.55V external supply is connected to PFBIN1 (pin 13) and PFBIN2 (pin 24). Furthermore, to lower the power consumption, the internal regulator should be powered down by writing ‘1’ to bit 15 of the VRCR register (0x00d0h).

When operating with dual supplies, follow these guidelines:

• When powering up, ramp up the 3.3V supply before the 1.55V supply.
• When powering down, turn off the 1.55V supply before turning off the 3.3V supply.
• Use the external RESET pin after power up to reset the PHY.
• To use the internal power-on reset, PFBIN1 and PFBIN2 must be operational less than 100ms after 3.3V rises to detect the internal RESET.

5.1.2.3 Variable IO Voltage

The TLK10xL digital IO pins can operate with a variable supply voltage. While the primary applications will use 3.3V, VDD_IO can also operate on 2.5V, and for MII mode only, VDD_IO of 1.8V can be used as well. For more details, see Section 4.6.

PIN NAME	TYPE	INTERNAL PU/PD		PIN NAME	TYPE	Internal PU/PD
TXD_3	IO	PD		COL (MLED(1))	IO	PU
TX_EN	IO	PD		RXD_0	IO	PD
INT/PWDN	IO	PU		RXD_1	IO	PD
LED_LINK (MLED(1))	IO	PU		RXD_2	IO	PD
MDIO	IO			RXD_3	IO	PD
RX_DV	IO	PD		TX_CLK	O
CRS	IO	PU		RX_CLK	O
RX_ER	IO	PU

Table 5-2 Auto-Negotiation Modes

AN_0	FORCED MODE
0	10Base-T, Half-Duplex 100Base-TX, Half-Duplex
1	10Base-T, Half or Full-Duplex 100Base-TX, Half or Full-Duplex

Table 5-3 PHY Address Mapping

PIN Number	PHYAD FUNCTION	RXD FUNCTION
29	PHYAD0	COL
30	PHYAD1	RXD_0
31	PHYAD2	RXD_1
32	PHYAD3	RXD_2
1	PHYAD4	RXD_3

Table 5-4 MLED Mode Select

(BIT 6:3)	MODE		(BIT 6:3)	MODE
0x0	Link OK		0x6	LED Speed: High for 10 Base TX
0x1	RX/TX Activity		0x7	Full Duplex
0x2	TX Activity		0x8	Link OK / Blink on TX/RX Activity
0x3	RX Activity		0x9	Active stretch signal
0x4	Collision		0xA	MI_LINK (100BT+FD)
0x5	LED Speed: High for 100 Base TX

Table 5-5 LED Mode Select

MODE	LED_CFG[0] (BIT 5) or (PIN 27)	LED_LINK
1	1	ON for Good Link OFF for No Link
2	0	ON for Good Link BLINK for Activity

5.1.9.1 Near-End Loopback

Near-end loopback provides the ability to loop the transmitted data back to the receiver via the digital or analog circuitry. The point at which the signal is looped back is selected using loopback control bits with several options being provided. Figure 5-5 shows the PHY near-end loopback functionality.

The Near-end Loopback mode is selected by setting the respective bit in the BIST Control Register (BISCR), MII register address 0x0016. MII loopback can be selected by using the BMCR register at address 0x0000, bit [14].

The Near-end Loopback can be selected according to the following:

• Reg 0x0000, Bit [14]: MII Loopback
• Reg 0x0016, Bit [0]: PCS input Loopback
• Reg 0x0016, Bit [1]: PCS output Loopback
• Reg 0x0016, Bit [2]: Digital Loopback
• Reg 0x0016, Bit [3]: Analog Loopback

Table 5-6 describes the available operational modes for each loop mode:

While in MII Loopback mode, there is no link indication, but packets propagate back to the MAC. While in MII Loopback mode the data is looped back, and can also be transmitted onto the media. For transmitting data during MII loopback in 100BT only please use bit [6] in the BISCR Register address 0x0016. For proper operation in Analog Loopback mode, attach 100Ω terminations to the RJ45 connector. External Loopback can be performed while working in normal mode (Bits 3:0 of the BISCR register are asserted to 0, and on the RJ45 connector, pin 1 is connected to pin 3 and pin 2 is connected to pin 6). To maintain the desired operating mode, Auto-Negotiation should be disabled before selecting Loopback mode. This constraint does not apply for external-loopback mode. For selected loopback Delay propagation timing please see Section 4.9.21.

5.1.9.2 Far-End Loopback

Far-end (Reverse) loopback is a special test mode to allow testing the PHY from the link-partner side. In this mode, data that is received from the link partner passes through the PHY's receiver, looped back on the MII and transmitted back to the link partner. Figure 5-6 shows Far-end loopback functionality.

The Reverse Loopback mode is selected by setting bit 4 in the BIST Control Register (BISCR), MII register address 0x0016.

While in Reverse Loopback mode the data is looped back and also transmitted onto the MAC Interface and all data signals that come from the MAC are ignored.

Table 5-7 describes the operating modes for Far-End Loopback.

5.1.11.1 TDR

The TLK10xL uses Time Domain Reflectometry (TDR) to determine the quality of the cables, connectors, and terminations in addition to estimating the cable length. Some of the possible problems that can be diagnosed include opens, shorts, cable impedance mismatch, bad connectors, termination mismatches, cross faults, cross shorts and any other discontinuities along the cable.

The TLK10xL transmits a test pulse of known amplitude (1V or 2.5V) down each of the two pairs of an attached cable. The transmitted signal continues down the cable and reflects from each cable imperfection, fault, bad connector, and from the end of the cable itself. After the pulse transmission the TLK10xL measures the return time and amplitude of all these reflected pulses. This technique enables measuring the distance and magnitude (impedance) of non-terminated cables (open or short), discontinuities (bad connectors), and improperly-terminated cables with ±1m accuracy.

The TLK10xL also uses data averaging to reduce noise and improve accuracy. The TLK10xL can record up to five reflections within the tested pair. If more than 5 reflections are recorded, the TLK10xL saves the first 5 of them. If a cross fault is detected, the TDR saves the first location of the cross fault and up to 4 reflections in the tested channel. The TLK10xL TDR can measure cables up to 200m in length.

For all TDR measurements, the transformation between time of arrival and physical distance is done by the external host using minor computations (such as multiplication, addition and lookup tables). The host must know the expected propagation delay of the cable, which depends, among other things, on the cable category (for example, CAT5, CAT5e, or CAT6).

TDR measurement is allowed in the TLK10xL in the following scenarios:

• While Link partner is disconnected – cable is unplugged at the other side
• Link partner is connected but remains “quiet” (for example, in power down mode)
• TDR could be automatically activated when the link fails or is dropped by setting bit 8 of register 0x0009 (CR1). The results of the TDR run after the link fails will be saved in the TDR registers. The SW could read these registers at any time to apply post processing on the TDR results. This mode is designed for cases in which the link dropped due to cable disconnections, in which after link failure, the line will be quiet to allow a proper function of the TDR.

5.1.11.2 ALCD

The TLK10xL also supports Active Link Cable Diagnostic (ALCD). The ALCD offers a passive method to estimate the cable length during active link. The ALCD uses passive digital signal processing based on adapted data, thus enabling measurement of cable length with an active link partner.

The ALCD Cable length measurement accuracy is ±5m for the pair used in the Rx path (due to the passive nature of the test, only the receive path is measured).

5.2.1.1 MII Transmit Error Code Forwarding

According to IEEE 802.3:

“If TX_EN is de-asserted on an odd nibble boundary, PHY should extend TX_EN by one TX_CLK cycle and behave as if TX_ER were asserted during that cycle”.

The TLK10xL supports Error Forwarding in MII transmission from the MAC to the PHY. Error forwarding allows adding information to the frame to be used as an error code between the 2 MACs. The error code informs the receiving MAC on the link partner side of the reason for the error from the transmitting side. If the MAC transmits an odd number of nibbles, an additional error nibble is added to the transmitted frame just before the end of the transmission.

To turn off Transmit Error Forwarding, write to bit 1 of register CR2 (0x000A). If Error Forwarding is disabled, delivered packets contain either odd or even numbers of nibbles.

In Figure 5-8, Error Code Forwarding functionality is illustrated. The wave diagram demonstrates MAC’s transmitted signals in one side and MAC’s reception signals on link partner side.

5.2.1.2 4-Bit to 5-Bit Encoding

The transmit data that is received from the MAC first passes through the 4-Bit to 5-Bit encoder. This block encodes 4-bit nibble into 5-bit code-groups according to the Table 5-8. Each 4-bit data nibble is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for control information or they are considered as not valid.

The code-group encoder substitutes the first 8-bits of the MAC preamble with a J/K code-group pair (11000 10001) upon transmission. The code-group encoder continues to replace subsequent 4-bit preamble and data nibbles with corresponding 5-bit code-groups. At the end of the transmit packet, upon the de-assertion of Transmit Enable signal from the MAC, the code-group encoder adds the T/R code-group pair (01101 00111) indicating the end of the frame.

After the T/R code-group pair, the code-group encoder continuously adds IDLEs into the transmit data stream until the next transmit packet is detected.

5.2.1.3 Scrambler

The purpose of the scrambler is to flatten the power spectrum of the transmitted signal, thus reduce EMI. The scrambler seed is generated with reference to the PHY address so that multiple PHYs that reside within the system will not use the same scrambler sequence.

5.2.1.4 NRZI and MLT-3 Encoding

To comply with the TP-PMD standard for 100Base-TX transmission over CAT-5 unshielded twisted pair cable, the scrambled data must be NRZI encoded. The serial binary data stream output from the NRZI encoder is further encoded to MLT-3. MLT-3 is a tri-level code where a change in the logic level represents a code bit '1' and the logic output remaining at the same level represents a code bit '0'.

5.2.1.5 Digital to Analog Converter

The multipurpose programmable transmit Digital to Analog Converter (DAC) receives digital coded symbols and generates filtered analog symbols to be transmitted on the line. In 100B-TX the DAC applies a low-pass shaping filter to minimize EMI. The DAC is designed to improve the return loss requirements and enable the use of low-cost transformers.

Digital pulse-shape filtering is also applied in order to conform to the pulse masks defined by standard and to reduce EMI and high frequency signal harmonics.

5.2.2.1 Analog Front End

The Receiver Analog Front End (AFE) resides in front of the 100B-TX receiver. The AFE consists of an Analog to Digital Converter (ADC), receive filters and a Programmable Gain Amplifier (PGA).

The ADC samples the input signal at the 125MHz clock recovered by the timing loop and feeds the data into the adaptive equalizer. The ADC is designed to optimize the SNR performance at the receiver input while maintaining high power-supply rejection ratio and low power consumption. There is only one ADC in the TLK10xL, which receives the analog input data from the relevant cable pair, according to MDI-MDIX resolution.

The PGA, digitally controlled by the adaptive equalizer, fully uses the dynamic range of the ADC by adjusting the incoming-signal amplitude. Generally, the PGA attenuates short-cable strong signals and amplifies long-cable weak signals.

5.2.2.2 Adaptive Equalizer

The adaptive equalizer removes Inter-Symbol Interference (ISI) from the received signal introduced by the channel and analog Tx/Rx filters. The TLK10xL includes both Feed Forward Equalization (FFE) and Decision Feedback Equalization (DFE). The combination of both adaptive modules with the adaptive gain control results in a powerful equalizer that can eliminate ISI and compensate for cable attenuation for longer-reach cables. In addition, the Equalizer includes a Shift Gear Step mechanism to provide fast convergence on the one hand and small residual-adaptive noise in steady state on the other hand.

5.2.2.3 Baseline Wander Correction

The DC offset of the transmitted signal is shifted down or up based on the polarity of the transmitted data because the MLT-3 data is coupled onto the CAT 5 cable through a transformer that is high-pass in nature. This phenomenon is called Baseline wander. To prevent corruption of the received data because of this phenomenon, the receiver corrects the baseline wander and can receive the ANSI TP-PMD-defined "killer packet" with no bit errors.

5.2.2.4 NRZI and MLT-3 Decoding

The TLK10xL decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI data. The NRZI-to-NRZ decoder is used to present NRZ-formatted data to the descrambler.

5.2.2.5 Descrambler

The descrambler is used to descramble the received NRZ data. The data is further deserialized and the parallelized data is aligned to 5-bit code-groups and mapped into 4-bit nibbles. At initialization, the 100B-TX descrambler uses the IDLE-symbols sequence to lock on the far-end scrambler state. During that time, neither data transmission nor reception is enabled. After the far-end scrambler state is recovered, the descrambler constantly monitors the data and checks whether it still synchronized. If, for any reason, synchronization is lost, the descrambler tries to re-acquire synchronization using the IDLE symbols.

5.2.2.6 5B/4B Decoder and Nibble Alignment

The code-group decoder functions as a look up table that translates incoming 5-bit code-groups into 4-bit nibbles. The code-group decoder first detects the Start of Stream Delimiter (SSD) /J/K/ code-group pair preceded by IDLE code-groups at the start of a packet. Once the code group alignment is determined, it is stored and used until the next start-of-frame. The decoder replaces the /J/K/ with the MAC preamble. Specifically, the /J/K/ 10-bit code-group pair is replaced by the nibble pair (0101 0101). All subsequent 5-bit code-groups are converted to the corresponding 4-bit nibbles for the duration of the entire packet. This conversion ceases upon the detection of the /T/R/ code-group pair denoting the End-of-Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups.

5.2.2.7 Timing Loop and Clock Recovery

The receiver must lock on the far-end transmitter clock in order to sample the data at the optimum timing. The timing loop recovers the far-end clock frequency and offset from the received data samples and tracks instantaneous phase drifts caused by timing jitter.

The TLK10xL has a robust adaptive-timing loop (Tloop) mechanism that is responsible for tracking the Far-End TX clock and adjusting the AFE sampling point to the incoming signal. The Tloop implements an advanced tracking mechanism that when combined with different available phases, always keeps track of the optimized sampling point for the data, and thus offers a robust RX path,tolerant to both PPM and Jitter. The TLK10xL is capable of dealing with PPM and jitter at levels far higher than those defined by the standard.

5.2.2.8 Phase-Locked Loops (PLL)

In 10B-T the digital phase lock loop (DPLL) function recovers the far-end link-partner clock from the received Manchester signal. The DPLL is able to combat clock jitter of up to ±18ns and frequency drifts of ±500ppm between the local PHY clock and the far-end clock. The DPLL feeds the decoder with a decoded serial bit stream.

The integrated analog Phase-Locked Loop (PLL) provides the clocks to the analog and digital sections of the PHY. The PLL is driven by an external reference clock (sourced at the XI,XO pins with a crystal oscillator, or at XI with an external reference clock).

5.2.2.9 Link Monitor

The TLK10xL implements the link monitor State Machine (SM) as defined by the IEEE 802.3 100Base-TX Standard. In addition, the TLK10xL enables several add-ons to the link monitor SM activated by configuration bits. The new add-ons include the recovery state which enables the PHY to attempt recovery in the event of a temporary energy-loss situation before entering the LINK_FAIL state, thus restarting the whole link establishment procedure. This sequence allows significant reduction of the recovery time in scenarios where the link loss is temporal.

In addition, the link monitor SM enables moving to the LINK_DOWN state based on descrambler synchronization failure and not only on Signal_Status indication, which shortens the drop-link down time. These add-ons are supplementary to the IEEE standard and are bypassed by default.

5.2.2.10 Signal Detect

The signal detect function of the TLK10xL is incorporated to meet the specifications mandated by the ANSIFDDI TP-PMD Standard as well as the IEEE 802.3 100Base-TX Standard for both voltage thresholds and timing parameters.

The energy-detector module provides signal-strength indication in various scenarios. Because it is based on an IIR filter, this robust energy detector has excellent reaction time and reliability. The filter output is compared to predefined thresholds in order to decide the presence or absence of an incoming signal.

The energy detector also implements hysteresis to avoid jittering in signal-detect indication. In addition it has fully-programmable thresholds and listening-time periods, enabling shortening of the reaction time if required.

5.2.2.11 Bad SSD Detection

A Bad Start of Stream Delimiter (Bad SSD) is any transition from consecutive idle code-groups to non-idle code-groups which is not prefixed by the code-group pair /J/K. If this condition is detected, the TLK10xL asserts RX_ER, and presents RXD[3:0] = 1110 to the MII for the cycles that correspond to received 5B code-groups until at least two IDLE code groups are detected. In addition, the FCSCR register (0x14h) is incremented by one for every error in the nibble.

When at least two IDLE code groups are detected, RX_ER and CRS are de-asserted.

5.2.3.1 10M Receive Input and Squelch

The squelch feature determines when valid data is present on the differential receive inputs. The TLK10xL implements a squelch to prevent impulse noise on the receive inputs from being mistaken for a valid signal. Squelch operation is independent of the 10Base-T operating mode. The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10Base-T standard) to determine the validity of data on the twisted-pair inputs.

The signal at the start of a packet is checked by the squelch, and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) are rejected. When this first squelch level is exceeded correctly, the opposite squelch level must then be exceeded no earlier than 50ns. Finally, the signal must again exceed the original squelch level no earlier than 50ns to qualify as a valid input waveform, and not be rejected. This checking procedure results in the typical loss of three preamble bits at the beginning of each packet. When the transmitter is operating, five consecutive transitions are checked before indicating that valid data is present. At this time, the squelch circuitry is reset.

5.2.3.2 Collision Detection

When in Half-Duplex mode, a 10Base-T collision is detected when receive and transmit channels are active simultaneously. Collisions are reported by the COL signal on the MII.

The COL signal remains set for the duration of the collision. If the PHY is receiving when a collision is detected, it is reported immediately (through the COL pin).

5.2.3.3 Carrier Sense

Carrier Sense (CRS) may be asserted due to receive activity after valid data is detected via the squelch function. For 10Mb/s Half Duplex operation, CRS is asserted during either packet transmission or reception. For 10Mb/s Full Duplex operation, CRS is asserted only during receive activity.

CRS is de-asserted following an end-of-packet.

5.2.3.4 Jabber Function

Jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condition. The jabber function monitors the TLK10xL output and disables the transmitter if it attempts to transmit a packet of longer than legal size. A jabber timer monitors the transmitter and disables the transmission if the transmitter is active for approximately 100ms.

When disabled by the Jabber function, the transmitter stays disabled for the entire time that the ENDEC module's internal transmit enable is asserted. This signal must be de-asserted for approximately 500ms (the unjab time) before the Jabber function re-enables the transmit outputs.

The Jabber function is only available and active in 10Base-T mode.

5.2.3.5 Automatic Link Polarity Detection and Correction

Swapping the wires within the twisted pair causes polarity errors. Wrong polarity affects the 10B-T PHYs. The 100B-TX is immune to polarity problems because it uses MLT3 encoding. The 10B-T automatically detects reversed polarity according to the received link pulses or data. Note that the default transmit link pulse polarity for the TLK10xL is reversed.

5.2.3.6 10Base-T Transmit and Receive Filtering

External 10Base-T filters are not required when using the TLK10xL, because the required signal conditioning is integrated into the device. Only isolation transformers and impedance matching resistors are required for the 10Base-T transmit and receive interface. The internal transmit filtering ensures that all the harmonics in the transmit signal are attenuated by at least 30dB.

5.2.3.7 10Base-T Operational Modes

The TLK10xL has two basic 10Base-T operational modes:

• Half Duplex mode – In Half Duplex mode the TLK10xL functions as a standard IEEE 802.3 10Base-T transceiver supporting the CSMA/CD protocol.
• Full Duplex mode – In Full Duplex mode the TLK10xL is capable of simultaneously transmitting and receiving without asserting the collision signal. The TLK10xL 10Mbs ENDEC is designed to encode and decode simultaneously.

5.2.4.1 Operation

Auto negotiation uses the 10B-T link pulses to encapsulate the transmitted data in a sequence of pulses, also referred to as a Fast Link Pulses (FLP) burst. The FLP Burst consists of a series of closely spaced 10B-T link integrity test pulses that form an alternating clock/data sequence. Extraction of the data bits from the FLP Burst yields a Link Code Word that identifies the operational modes supported by the remote device, as well as some information used for the auto negotiation function’s handshake mechanism.

The information exchanged between the devices during the auto-negotiation process consists of the devices' abilities such as duplex support and speed. This information allows higher levels of the network (MAC) to send to the other link partner vendor-specific data (via the Next Page mechanism, see below), and provides the mechanism for both parties to agree on the highest performance mode of operation.

When auto negotiation has started, the TLK10xL transmits FLP on one twisted pair and listens on the other, thus trying to find out whether the other link partner supports the auto negotiation function as well. The decision on what pair to transmit/listen depends on the MDI/MDI-X state. If the other link partner activates auto negotiation, then the two parties begin to exchange their information. If the other link partner is a legacy PHY or does not activate the auto negotiation, then the TLK10xL uses the parallel detection function, as described in IEEE802.3 chapters 40 and 28, to determine 10B-T or 100B-TX operation modes.

5.2.4.2 Initialization and Restart

The TLK10xL initiates the auto negotiation function if one of the following events have happened:

1. Hardware reset de-assertion
2. Software reset (via register)
3. Auto negotiation restart (via register BMCR (0x0000h) bit 9)
4. Power-up sequence (via register BMCR (0x0000h) bit 11)

The auto-negotiation function is also initiated when the auto-negotiation enable bit is set in register BMCR (0x0000h) bit 12 and one of the following events has happened:

1. Software restart
2. Transitioning to link_fail state, as described in IEEE802.3

To disable the auto-negotiation function during operation, clear register BMCR (0x0000h) bit 12. During operation, setting/resetting this register does not affect the TLK10xL operation. For the changes to take place, issue a restart command through register BMCR (0x0000h) bit 9.

5.2.4.3 Next Page Support

The TLK10xL supports the optional feature of the transmission and reception of auto-negotiation additional (vendor specific) next pages.

If next pages are needed, the user must set register ANAR(0x0004h) bit 15 to '1'. The next pages are then sent and received through registers ANNPTR(0x0007h) and ANLNPTR(0x0008h), respectively. The user must poll register ANER(0x0006h) bit 1 to check whether a new page has been received, and then read register ANLNPTR for the received next page's content. Only after register ANLNPTR is read may the user write to register ANNPTR the next page to be transmitted. After register ANNPTR is written, new next pages overwrite the contents of register ANLNPTR.

If register ANAR(0x0004h) bit 15 is set, then the next page sequence is controlled by the user, meaning that the auto-negotiation function always waits for register ANNPTR to be written before transmitting the next page.

If additional user-defined next pages are transmitted and the link partner has more next pages to send, it is the user's responsibility to keep writing null pages (of value 0x2001) to register ANNPTR until the link partner notifies that it has sent its last page (by setting bit 15 of its transmitted next page to zero).

Table 5-9 Register Map

OFFSET HEX	ACCESS	TAG	DESCRIPTION
00h	RW	BMCR	Basic Mode Control Register
01h	RO	BMSR	Basic Mode Status Register
02h	RO	PHYIDR1	PHY Identifier Register 1
03h	RO	PHYIDR2	PHY Identifier Register 2
04h	RW	ANAR	Auto-Negotiation Advertisement Register
05h	RO	ANLPAR	Auto-Negotiation Link Partner Ability Register
06h	RO	ANER	Auto-Negotiation Expansion Register
07h	RW	ANNPTR	Auto-Negotiation Next Page TX
08h	RO	ANLNPTR	Auto-Negotiation Link Partner Ability Next Page Register
09h	RW	CR1	Control Register 1
0Ah	RW	CR2	Control Register 2
0Bh	RW	CR3	Control Register 3
0Ch	RW	RESERVED	RESERVED
0Dh	RW	REGCR	Register control register
0Eh	RW	ADDAR	Address or Data register
0Fh	RW	FLDS	Fast Link Down Status
0x0010	RO	PHYSTS	PHY Status Register
0x0011	RW	PHYSCR	PHY Specific Control Register
0x0012	RW	MISR1	MII Interrupt Status Register 1
0x0013	RW	MISR2	MII Interrupt Status Register 2
0x0014	RO	FCSCR	False Carrier Sense Counter Register
0x0015	RO	RECR	Receive Error Count Register
0x0016	RW	BISCR	BIST Control Register
0x0017	RO	RBR	RMII and Status Register
0x0018	RW	LEDCR	LED Control Register
0x0019	RW	PHYCR	PHY Control Register
0x001A	RW	10BTSCR	10Base-T Status/Control Register
0x001B	RW	BICSR1	BIST Control and Status Register 1
0x001C	RO	BICSR2	BIST Control and Status Register 2
0x001D	RW	RESERVED	RESERVED
0x001E	RW	CDCR	Cable Diagnostic Control Register
0x001F	RW	PHYRCR	PHY Reset Control Register
EXTENDED REGISTERS
0x0020- 0x0024	RW	RESERVED	RESERVED
0x0025	RW	MLEDCR	Multi LED Control register
0x0026	RW	RESERVED	RESERVED
0x0027	RW	COMPTR	Compliance Test register
0x0028- 0x003CD	RW	RESERVED	RESERVED
0x003E	RW	PTPPSEL	IEEE1588 Precision Timing Pin Select
0x003F	RW	PTPCFG	IEEE1588 Precision Timing Configuration
0x0040	RW	RESERVED	RESERVED
0x0041	RW	RESERVED	RESERVED
0x0042	RO	TXCPSR	TX_CLK Phase Shift Register
0x0043- 0x00AD	RW	RESERVED	RESERVED
0x00AE	RW	PWRBOCR	Power Back Off Control Register
0x00AF- 0x00CF	RW	RESERVED	RESERVED
0x00D0	RW	VRCR	Voltage Regulator Control Register
0x00D1-0x0154	RW	RESERVED	RESERVED
0x0155	RW	ALCDRR1	ALCD Control and Results 1
0x0156- 0x016F	RW	RESERVED	RESERVED
0x0170	RW	CDSCR1	Cable Diagnostic Specific Control Register 1
0x0171	RW	CDSCR2	Cable Diagnostic Specific Control Register 2
0x0172	RW	RESERVED	RESERVED
0x0173	RW	CDSCR3	Cable Diagnostic Specific Control Register 3
0x0174-0x0176	RW	RESERVED	RESERVED
0x0177	RW	CDSCR4	Cable Diagnostic Specific Control Register 4
0x0178- 0x017F	RW	RESERVED	RESERVED
0x0180	RO	CDLRR1	Cable Diagnostic Location Result Register 1
0x0181	RO	CDLRR2	Cable Diagnostic Location Result Register 2
0x0182	RO	CDLRR3	Cable Diagnostic Location Result Register 3
0x0183	RO	CDLRR4	Cable Diagnostic Location Result Register 4
0x0184	RO	CDLRR5	Cable Diagnostic Location Result Register 5
0x0185	RO	CDLAR1	Cable Diagnostic Amplitude Result Register 1
0x0186	RO	CDLAR2	Cable Diagnostic Amplitude Result Register 2
0x0187	RO	CDLAR3	Cable Diagnostic Amplitude Result Register 3
0x0188	RO	CDLAR4	Cable Diagnostic Amplitude Result Register 4
0x0189	RO	CDLAR5	Cable Diagnostic Amplitude Result Register 5
0x018A	RW	CDGRR	Cable Diagnostic General Result Register
0x018B-0x0214	RW	RESERVED	RESERVED
0x0215	RW	ALCDRR2	ALCD Control and Results 2 Register
0x021D	RW	ALCDRR3	ALCD Control and Results 3 Register

Table 5-10 Register Table

REGISTER NAME	ADDR	TAG	BIT 15	BIT 14	BIT 13	BIT 12	BIT 11	BIT 10	BIT 9	BIT 8	BIT 7	BIT 6	BIT 5	BIT 4	BIT 3	BIT 2	BIT 1	BIT 0
Basic Mode Control Register	00h	BMCR	Reset	Loopback	Speed Selection	Auto-Neg Enable	IEEE Power Down	Isolate	Restart Auto-Neg	Duplex Mode	Collision Test	Reserved
Basic Mode Status Register	01h	BMSR	100Base -T4	100Base -TX FDX	100Base -TX HDX	10Base-T FDX	10Base-T HDX	Reserved				MF Preamble Suppress	Auto-Neg Complete	Remote Fault	Auto-Neg Ability	Link Status	Jabber Detect	Extended Capability
PHY Identifier Register 1	02h	PHYIDR 1	OUI MSB
PHY Identifier Register 2	03h	PHYIDR 2	OUI LSB						VNDR_ MDL						MDL_ REV
Auto-Negotiation Advertisement Register	04h	ANAR	Next Page Ind	Reserved	Remote Fault	Reserved	ASM_DI R	PAUSE	100B-T4	100B-TX_FD	100B-TX	10B-T_FD	10B-T	Protocol Selection[4:0]
Auto-Negotiation Link Partner Ability Register (Base Page)	05h	ANLPAR	Next Page Ind	ACK	Remote Fault	Reserved	ASM_DI R	PAUSE	100B-T4	100B-TX_FD	100B-TX	10B-T_FD	10B-T	Protocol Selection[4:0]
Auto-Negotiation Expansion Register	06h	ANER	Reserved											PDF	LP_NP_ ABLE	NP_ ABLE	PAGE_ RX	LP_AN_ABLE
Auto-Negotiation Next Page TX Register	07h	ANNPTR	Next Page Ind	Reserved	Message Page	ACK2	TOG_TX	CODE
Auto-Negotiate Link Partner Ability Page Register	08h	ANLNPTR	Next Page Ind	Reserved	Message Page	ACK2	Toggle	CODE
Control Register 1	09h	CR1	Reserved						RMII Enhance Mode	TDR Auto Run	Link Loss Recovery	Fast Auto MDI/X	Robust Auto MDI/X	Fast AN Enable	Fast AN Select		Fast RXDV Detect	Reserved
Control Register 2	0Ah	CR2	100BT Force Far-End Link drop	Reserved								Fast Link-Up in PD	Extended FD Ability	Enhance LED Link	Isolate MII in 100BT HD	RXERR During IDLE	Odd Nibble Detect Disable	RMII Receive Clock
Control Register 3	0Bh	CR3	Reserved					Fast Link Down Mode	Reserved			Polarity Swap	MDI/X Swap	Reserved	Fast Link Down Sel
Register Control Register	0Dh	REGCR	Function		Reserved									DEVICE ADDRESS
Address or Data Register	0Eh	ADDAR	Addr/ Data
Fast Link Down Status	0Fh	FLDS	Reserved							Fast Link Down Status[4:0]					Reserved
PHY Status Register	10h	PHYSTS	Reserved	MDI-X Mode	Receive Err Latch	Polarity Status	False Carrier Sen Latch	Signal Detect	Descramb Lock	Page Receive	MII Interrupt	Remote Fault	Jabber Detect	Auto-Neg Status	Loopback Status	Duplex Status	Speed Status	Link Status
PHY Specific Control Register	11h	PHYSCR	Disable PLL	Power Save Enable	Power Save Mode		Scrambler Bypass	Reserved	Loopback Fifo Depth		Reserved			COL FD Enable	INT POL	TINT	INT_EN	INT_OE
MII Interrupt Status Register 1	12h	MISR1	Reserved		Link Status INT	Speed INT	Duplex Mode INT	Auto-Neg Comp INT	FC HF INT	RE HF INT	Reserved		Link Status En	Speed EN	Duplex Mode En	Auto-Neg Comp En	FC HF En	RE HF En
MII Interrupt Status Register 2	13h	MISR2	Reserved	Auto-Neg Error INT	Page Received INT	Loopback FIFO O/U INT	MDI Crossover INT	Sleep Mode INT	Polarity INT	Jabber INT	Reserved	Auto-Neg Error EN	Page Received EN	Loopback FIFO O/U EN	MDI Crossover EN	Sleep Mode EN	Polarity EN	Jabber EN
MII Interrupt Control Register	14h	FCSCR	Reserved								FCS Count
Receive Error Counter Register	15h	RECR	RX Err Count
BIST Control Register	16h	BISCR	Reserved	PRBS Count Mode	Generate PRBS Packets	Packet Gen Enable	PRBS Checker Lock	PRBS Checker SyncLoss	Packet Gen Status	Power Mode	Reserved	Transmit in MII Loopback	Reserved	Loopback Mode
RMII Control, Status Register	17h	RCSR	Reserved										RMII Mode	RMII Revision	RMII OVF Status	RMII UNF Status	ELAST BUF
LED Control Register	18h	LEDCR	Reserved					Blink Rate		LED Speed Polarity	LED Link Polarity	LED Activity Polarity	Drive LED Speed	Drive LED Link	Drive LED Activity	Speed LED ON/OFF	Link LED ON/OFF	Activity LED ON/OFF
PHY Control Register	19h	PHYCR	Auto MDI/X Enable	Force MDI/X	Pause RX Status	Pause TX Status	MI Link Status	Reserved			Bypass LED Stretching	LED CFG		PHY ADDR
BIST Packet Length register	1Ah	10BTSCR	Reserved		Receiver TH	Squelch				Reserved	NLP Disable	Reserved		Polarity Status	Reserved			Jabber Disable
BIST Control, Status Register 1	1Bh	BICSR1	BIST Err Count								BIST IPG Length
BIST Control, Status Register 2	1Ch	BICSR2	Reserved					Packet Length
Cable Diagnostic Control Register	1Eh	CDCR	Diagnostic Start	Reserved					Link Quality	Link Quality	Reserved						Diagnostic Done	Diagnostic Fail
Power Down Register	1Fh	PDR	Software Reset	Software Restart	Reserved

Table 5-11 Register Table, Extended Registers

Register Name	Addr	Tag	Bit 15	Bit 14	Bit 13	Bit 12	Bit 11	Bit 10	Bit 9	Bit 8	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
Multi LED Control	25h	MLED	Reserved					MLED pin 29 Route, Enable (COL Disable)	MLED Polarity	Reserved		MLED Configuration				Reserved	MLED pin 17 Routing Cnfig.	"MLED pin Routing enable"
Compliance Test Register	27h	COMPTR	Reserved										Test Mode Select	Test Configuration
1588 PTP Pin Select	3Eh	PTPPSEL	Reserved									cfg_1588_TX_pin_sel			Reserved	cfg_1588_RX_pin_sel
1588 PTP Config	3Fh	PTPCFG	cfg_1588_TX_set_phase			cfg_1588_RX_set_phase			cfg_TX_ERR_sel		Reserved
TX_CLK	42h	TXCPSR	Reserved											Phase Shift En	Phase Shift Value
Voltage Regulator Control Register	D0h	VRCR	VRPD	Reserved
PowerBack Off Control Register	AEh	PWRBOCR	Reserved							PowerBack Off			Reserved
ALCD Control and Results 1	155h	ALCDRR1	alcd_start	Reserved		alcd_done	alcd_out1								Reserved	alcd_ctrl
Cable Diagnostic Specific Control Register 1	170h	CDSCR1	Reserved	Cross Disable	TPTD Bypass	TPRD Bypass	Reserved	Average Cycles			Reserved
Cable Diagnostic Specific Control Register 2	171h	CDSCR2	Reserved												TDR pulse control
Cable Diagnostic Specific Control Register 3	173h	CDSCR3	Cable length								Reserved
Cable Diagnostic Specific Control Register 4	177h	CDSCR4				Short cables TH					Reserved
Cable Diagnostic Location Results Register 1-5	180h	CDLRR1	TPTD/RD Peak Location
	181h	CDLRR2
	182h	CDLRR3
	183h	CDLRR4
	184h	CDLRR5
Cable Diagnostic Amplitude Results Register 1-5	185h	CDLAR1	Reserved	TPTD/RD Peak Amplitude							Reserved	TPTD/RD Peak Amplitude
	186h	CDLAR2
	187h	CDLAR3
	188h	CDLAR4
	189h	CDLAR5
Cable Diagnostic General Results	18Ah	CDGRR	TPTD Peak Polarity 5	TPTD Peak Polarity 4	TPTD Peak Polarity 3	TPTD Peak Polarity 2	TPTD Peak Polarity 1	TPRD Peak Polarity 5	TPRD Peak Polarity 4	TPRD Peak Polarity 3	TPRD Peak Polarity 2	TPRD Peak Polarity 1	Cross Detect on TPTD	Cross Detect on TPRD	Above 5 TPTD Peaks	Above 5 TPTD Peaks	Reserved	Reserved
ALCD Control and Results 2	215h	ALCDRR2	Reserved												alcd_out2
ALCD Control and Results 3	21Dh	ALCDRR3	Reserved				FAGC Accumulator

5.3.1.1 Basic Mode Control Register (BMCR)

5.3.1.2 Basic Mode Status Register (BMSR)

5.3.1.3 PHY Identifier Register 1 (PHYIDR1)

The PHY Identifier Registers 1 and 2 together form a unique identifier for the TLK10xL. The identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. The Texas Instruments IEEE-assigned OUI is 080028h, implemented as Reg 0x2 [15:0] = OUI[21:6] = 2000(h) and Reg 0x3 [15:10] = OUI[5:0] = A(h).

5.3.1.4 PHY Identifier Register 2 (PHYIDR2)

5.3.1.5 Auto-Negotiation Advertisement Register (ANAR)

This register contains the advertised abilities of this device as they are transmitted to its link partner during Auto-Negotiation.

5.3.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)

This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported.

5.3.1.7 Auto-Negotiate Expansion Register (ANER)

This register contains additional Local Device and Link Partner status information.

5.3.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)

This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.

5.3.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)

This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.

5.3.1.10 Control register 1 (CR1)

5.3.1.11 Control register 2 (CR2)

5.3.1.12 Control Register 3 (CR3)

5.3.1.13 Extended Register Addressing

REGCR (0x000D) and ADDAR (0x000E) allow read/write access to the extended register set (addresses above 0x001F) using indirect addressing.

• REGCR [15:14] = 00: A write to ADDAR modifies the extended register set address register. This address register must be initialized in order to access any of the registers within the extended register set.
• REGCR [15:14] = 01: A read/write to ADDAR operates on the register within the extended register set selected (pointed to) by the value in the address register. The address register contents (pointer) remain unchanged.
• REGCR [15:14] = 10: A read/write to ADDAR operates on the register within the extended register set selected (pointed to) by the value in the address register. After that access is complete, for both reads and writes, the value in the address register is incremented.
• REGCR [15:14] = 11: A read/write to ADDAR operates on the register within the extended register set selected (pointed to) by the value in the address register. After that access is complete, for write accesses only, the value in the address register is incremented. For read accesses, the value of the address register remains unchanged.

5.3.1.14 Fast Link Down Status Register

5.3.1.15 PHY Status Register (PHYSTS)

This register provides quick access to commonly accessed PHY control status and general information.

5.3.1.16 PHY Specific Control Register (PHYSCR)

This register implements the PHY Specific Control register. This register allows access to general functionality inside the PHY to enable operation in reduced power modes and control interrupt mechanism.

5.3.1.17 MII Interrupt Status Register 1 (MISR1)

This register contains events status and enables for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt will be generated if the event occurs. The PHYSCR register (0x0011) bits 1 and 0 must also be set to allow interrupts. The status indications in this register will be set even if the interrupt is not enabled.

5.3.1.18 MII Interrupt Status Register 2 (MISR2)

This register contains events status and enables for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt will be generated if the event occurs. The PHYSCR register (0x0011) bits 1 and 0 must also be set to allow interrupts. The status indications in this register will be set even if the interrupt is not enabled.

5.3.1.19 False Carrier Sense Counter Register (FCSCR)

This counter provides information required to implement the "False Carriers" attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification.

5.3.1.20 Receiver Error Counter Register (RECR)

This counter provides information required to implement the "Symbol Error During Carrier" attribute within the PHY managed object class of Clause 30 of the IEEE 802.3u specification.

5.3.1.21 BIST Control Register (BISCR)

This register is used for Build-In Self Test (BIST) configuration. The BIST functionality provides Pseudo Random Bit Stream (PRBS) mechanism including packet generation generator and checker. Selection of the exact loopback point in the signal chain is also done in this register.

5.3.1.22 RMII Control and Status Register (RCSR)

This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed.

5.3.1.23 LED Control Register (LEDCR)

This register provides the ability to directly manually control the Link LED output.

5.3.1.24 PHY Control Register (PHYCR)

This register provides the ability to control and set general functionality inside the PHY.

5.3.1.25 10Base-T Status/Control Register (10BTSCR)

This register provides the ability to control and read status of the PHY’s internal 10Base-T functionality.

5.3.1.26 BIST Control and Status Register 1 (BICSR1)

This register provides the total number of error bytes that was received by the PRBS checker and defines the Inter packet Gap (IPG) for the packet generator.

5.3.1.27 BIST Control and Status Register2 (BICSR2)

This register allows programming the length of the generated packets in bytes for the BIST mechanism.

Cable Diagnostic Control Register (CDCR), address 0x001E

BIT	BIT NAME	DEFAULT	DESCRIPTION
15	Diagnostic Start	0, RW	Cable Diagnostic Process Start: 1 = Start execute cable measurement 0 = Cable Diagnostic is disabled Diagnostic Start bit is cleared with raise of Diagnostic Done indication.
14:10	RESERVED	000 00, RO	RESERVED: Writes ignored, read as 0.
9:8	Link Quality	00, RO	Link Quality Indication 00 = Reserved 01 = Good Quality Link Indication 10 = Mid Quality Link Indication 11 = Poor Quality Link Indication The value of these bits are valid only when link is active – While reading “1” from “Link Status” bit 0 on PHYSTS register (0x0010).
7:4	RESERVED	0000, RO	RESERVED: Writes ignored, read as 0.
3:2	RESERVED	00, RO	RESERVED: Writes ignored, read as 0.
1	Diagnostic Done	0, RO	Cable Diagnostic Process Done: 1 = Indication that cable measurement process completed 0 = Diagnostic has not completed
0	Diagnostic Fail	0, RO	Cable Diagnostic Process Fail: 1 = Indication that cable measurement process failed 0 = Diagnostic has not failed

Table 5-40 PHY Reset Control Register (PHYRCR), address 0x001F

BIT	BIT NAME	DEFAULT	DESCRIPTION
15	Software Reset	0, RW,SC	Software Reset: 1 = Reset PHY. This bit is self cleared and has same effect as Hardware reset pin. 0 = Normal Operation
14	Software Restart	0, RW,SC	Software Restart: 1 = Reset PHY. This bit is self cleared and resets all PHY circuitry except the registers. 0 = Normal Operation
13:0	RESERVED	00 0000 0000 0000, RO	Writes ignored, read as 0

Table 5-41 Multi LED Control register (MLEDCR), address 0x0025

BIT	BIT NAME	DEFAULT	DESCRIPTION
15:11	RESERVED	0000 0, RO	Writes ignored, read as 0
10	MLED pin 29 Route & Enable (COL Disable)	0, RW	Disable collision pin, and enable and route MLED (Multi LED) output to pin 29 Default - LINK advertise, LED_CFG strap can change to LINK+ACT
9	MLED Polarity RW Strap	RW, Strap	The polarity of MLED depends on the routing configuration and the strap being used on the selected pin. If the pin is strapped high via a pull-up resistor, the LED will be active low. If the pin is strapped low via a pull-down resistor, the LED will be active high.
8:7	RESERVED	0 0, RW, SC	RESERVED
6:3	MLED Configuration	000 0, RW	0000 = Link OK 0001 = RX/TX Activity 0010 = TX Activity 0011 = RX Activity 0100 = Collision 0101 = Speed: High for 100 Base TX 0110 = Speed: High for 10 Base TX 0111 = Full Duplex 1000 = Link OK / Blink on TX/RX Activity 1001 = Active Stretch Signal 1010 = MII LINK (100BT+FD)
2	RESERVED	0, RW	Writes ignored, read as 0.
1	MLED pin 17 Routing Cnfig.	0, RW	Route MLED to pin 17 (requires bit[0] to be enabled)
0	MLED pin Routing enable	0, RW	Enable routing for MLED according to MLED pin routing config

Table 5-42 Compliance Test register (COMPTR), address 0x0027

BIT	BIT NAME	DEFAULT	DESCRIPTION
15:6	RESERVED	0000 0000 00, RO	Writes ignored, read as 0
5	Test Mode Select	0, RW	MSB bit for 100Base-TX test mode. Note: bit 4 must be '0' for 100Base-TX test modes.
4:0	Test Configuration	0 0000, RW	Bit 4 enables 10Base-T test modes. 1 = 10Base-T test modes 0 = 100Base-TX test modes
			For 10Base-T testing, bits [3:0] select the 10Base-T pattern as follows: 0000 = Single NLP 0000 = Single NLP 0001 = Single Pulse 1 0010 = Single Pulse 0 0011 = Repetitive 1 0100 = Repetitive 0 0101 = Preamble (repetitive '10') 0110 = Single 1 followed by TP_IDLE 0111 = Single 0 followed by TP_IDLE 1000 = Repetitive '1001' sequence 1001 = Random 10Base-T data 1010 = TP_IDLE_00 1011 = TP_IDLE_01 1100 = TP_IDLE_10 1101 = TP_IDLE_11 1001 = Random 10Base-T data
			For 100Base-TX testing, bits {5,[3:0]} select the transmit sequence. The test mode transmits a repetitive sequence consisting of a '1' followed by a configurable number of '0' bits. Bits {5,[3:0]} define the number of '0' bits that follow the '1'. 1 to 31 '1' bits may be selected. 0,0001 - 1,1111: single '0' to 31 zeroes 0,0000: Clear the register
			Note 1: Bit 4 must be '0' for 100Base-TX test modes. Note 2: 100Base-T test modes must be cleared before applying a new value. Bits {5,[3:0]} must be written to 0x0 before configuring a new value. Note 3: When performing 100Base-TX or 10Base-T tests, the speed must be forced using the Basic Mode Control Register (BMCR), address 0x0000.

Table 5-43 IEEE1588 Precision Timing Pin Select (PTPPSEL), address 0x003E

BIT	BIT NAME	DEFAULT	DESCRIPTION
15:7	RESERVED	<0000 0>, RO	RESERVED: Writes ignored, read as 0.
6:4	cfg_1588_TX_pin_sel	0, RW	IEEE 1588 TX Pin Select: Assigns transmit SFD pulse indication to pin selected by value in column at right.	001 - LED_ACT Pin 010 - LED_SPEED Pin 011 - LED_LINK Pin 100- CRS Pin 101 - COL Pin 110 - PWDNN/INT Pin 111 - No pulse output
3	RESERVED	0, RO	RESERVED: Writes ignored, read as 0.
2:0	cfg_1588_RX_pin_sel	0, RW	IEEE 1588 RX Pin Select: Assigns receive SFD pulse indication to pin selected by value in column at right.

Table 5-44 IEEE1588 Precision Timing Configuration (PTPCFG), address 0x003F

BIT	BIT NAME	DEFAULT	DESCRIPTION
15:13	cfg_1588_TX_set_phase	<101>, RW	PTP Transmit Timing: Set 1588 indication for TX path (8ns step)
12:10	cfg_1588_RX_set_phase	<101>, RW	PTP Receive TIming: Set 1588 indication for RX path (8ns step)
9:8	cfg_TX_ERR_sel	0, (TRIM)	Configure TX ERR Input Pin: 00 - No TX ERR 01 - Use LED ACT as TX_ERR 10 - Use PWRDN as TX_ERR 11 - USe COL as TX_ERR
7:0	RESERVED	<0100 0100>, RW	RESERVED

Table 5-45 TX_CLK Phase Shift Register (TXCPSR), address 0x0042

BIT	BIT NAME	DEFAULT	DESCRIPTION
15:5	RESERVED	0000 0000 000, RO	RESERVED: Writes ignored, read as 0
4	Phase Shift Enable	0,RW,SC	TX Clock Phase Shift Enable: 1 = Perform Phase Shift to the TX_CLK according to the value written to Phase Shift Value in bits [4:0]. 0 = No change in TX Clock phase
3:0	Phase Shift Value	0000,RW	TX Clock Phase Shift Value: The value of this register represents the current phase shift between Reference clock at XI and MII Transmit Clock at TX_CLK. Any different value that will be written to these bits will shift TX_CLK by 4 times the difference (in nSec). For example, if the value of this register is 0x2, Writing 0x9 to this register shifts TX_CLK by 28nS (4 times 7).However, since the maximum difference between XI and TX_CLK could be 40nSec (value of 10) in case of writing value bigger than 10, the updated value is the written value modulo 10.

Table 5-46 Power Back Off Control Register (PWRBOCR), address 0x00AE

BIT	BIT NAME	DEFAULT	DESCRIPTION
15	RESERVED	1, RO	RESERVED
14	RESERVED	0, RO	RESERVED
13:9	RESERVED	00 000, RO	RESERVED
8:6	Power Back Off	0, RW	Power Back Off Level: See Application Note SLLA328 000 = Normal Operation 001 = Level 1 (up to 140m cable between TLK link partners) 010 = Level 2 (up to 100m cable between TLK link partners) 011 = Level 3 (up to 80m cable between TLK link partners) Others = Reserved
5:0	RESERVED	10 0000, RO	RESERVED

Table 5-47 Voltage Regulator Control Register (VRCR), address 0x00D0

BIT	BIT NAME	DEFAULT	DESCRIPTION
15	VRPD	0, RW, SC	Voltage Regulator Power Down: 1 = Power Down. Allow the system to power down the voltage regulator block of the PHY using register access. 0 = Normal Operation. Voltage Regulator is powered and outputs voltage on the PFBOUT pin.
14:0	RESERVED	000 0000 0000, RW	RESERVED: Must be written as 0.

5.3.11.1 ALCD Control and Results 1 (ALCDRR1)

5.3.11.2 Cable Diagnostic Specific Control Registers (CDSCR1 - CDSCR4)

Use CDSCR1 to select the channel for the cable diagnostics test. CDSCR1 contains the enable and bypass bits for the diagnostic tests, and defines the number of executed and averaged TDR sequences. CDSCR2 - CDSCR4 configure other parameters for cable diagnostics.

5.3.11.3 Cable Diagnostic Location Results Register 1 (CDLRR1)

This register provides the peaks locations after execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

5.3.11.4 Cable Diagnostic Location Results Register 2 (CDLRR2)

This register provides the peaks locations after execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

5.3.11.5 Cable Diagnostic Location Results Register 3 (DDLRR3)

This register provides the peaks locations after execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

5.3.11.6 Cable Diagnostic Location Results Register 4 (CDLRR4)

This register provides the peaks locations after execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

5.3.11.7 Cable Diagnostic Location Results Register 5 (CDLRR5)

This register provides the peaks locations after execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

5.3.11.8 Cable Diagnostic Amplitude Results Register 1 (CDARR1)

This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

5.3.11.9 Cable Diagnostic Amplitude Results Register 2 (CDARR2)

This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

5.3.11.10 Cable Diagnostic Amplitude Results Register 3 (CDARR3)

This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

5.3.11.11 Cable Diagnostic Amplitude Results Register 4 (CDARR4)

This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

5.3.11.12 Cable Diagnostic Amplitude Results Register 5 (CDARR5)

This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

5.3.11.13 Cable Diagnostic General Results Register (CDGRR)

This register provides general measurement results after the execution of the TDR. The Cable Diagnostic software should post process this result together with other Peaks’ location and amplitude results.

5.3.11.14 ALCD Control and Results 2 (ALCDRR2)

5.3.11.15 ALCD Control and Results 3 (ALCDRR3)