9.3.1 Rail-to-Rail Input Operation

The TLV237x input stage consists of two differential transistor pairs (NMOS and PMOS) that operate together to achieve rail-to-rail input operation. The transition point between these two pairs are shown in Figure 1, Figure 2, and Figure 3 for a 2.7-V, 5-V, and 15-V supply. As the common-mode input voltage approaches the positive supply rail, the input pair switches from the PMOS differential pair to the NMOS differential pair. This transition occurs approximately 1.35 V from the positive rail and results in a change in offset voltage due to different device characteristics between the NMOS and PMOS pairs. If the input signal to the device is large enough to swing between both rails, this transition results in a reduction in common-mode rejection ratio (CMRR). If the input signal does not swing between both rails, bias the signal in the region where only one input pair is active. This is the region in Figure 1 and Figure 3 where the offset voltage varies slightly across the input range and optimal CMRR can be achieved. This has the greatest impact when operating from a 2.7-V supply voltage.