11.1 Layout Guidelines

• All decoupling capacitors must be located as close as possible to the loads they are supplying.
• TI recommends large copper fill areas or thick traces wherever possible to provide low inductance current paths between decoupling capacitors and their loads
• Ensure that there are no vias or discontinuities in the forward or return current paths that can cause the current loop area and therefore the loop inductance to increase.
• For high-frequency current paths routed across PCB layers, multiple vias can be placed close together (but not obstructing the current path) to lower inductance.

11.2 Layout Example

Figure 43. Layout Example Schematic