SLAS354C September   2001  – September 2015 TLV2553

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  External Reference Specifications
    7. 6.7  Operating Characteristics
    8. 6.8  Timing Requirements: VREF+ = 5 V
    9. 6.9  Timing Requirements: VREF+ = 2.5 V
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog MUX
      2. 8.3.2 Reference
    4. 8.4 Device Functional Modes
      1. 8.4.1  Converter Operation
      2. 8.4.2  Data I/O Cycle
      3. 8.4.3  Sampling Cycle
      4. 8.4.4  Conversion Cycle
      5. 8.4.5  Power Up and Initialization
        1. 8.4.5.1 Example
      6. 8.4.6  Data Input
      7. 8.4.7  Data Input—Address/Command Bits
      8. 8.4.8  Data Output Length
      9. 8.4.9  LSB Out First
      10. 8.4.10 Bipolar Output Format
      11. 8.4.11 EOC Output
      12. 8.4.12 Chip-Select Input (CS)
      13. 8.4.13 Power-Down Features
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

DW or PW Package
20-Pin SOIC or TSSOP
Top View
TLV2553 po_01_slas354.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AIN0 to AIN10 1 to 9, 11, 12 I Analog input. These 11 analog-signal inputs are internally multiplexed.
CS 15 I Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT, DATA IN, and I/O CLOCK. A low-to-high transition disables DATA IN and I/O CLOCK within a setup time.
DATA IN 17 I Serial data input. The 4-bit serial data can be used as address selects the desired analog input channel or test voltage to be converted next, or a command to activate other features. The input data is presented with the MSB (D7) first and is shifted in on the first four rising edges of the I/O CLOCK. After the four address/command bits are read into the command register CMR, I/O CLOCK clocks the remaining four bits of configuration in.
DATA OUT 16 O 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state and is driven to the logic level corresponding to the MSB/LSB value of the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next MSB/LSB, and the remaining bits are shifted out in order.
EOC 19 O End-of-convertions status. Used to indicate the end of conversion (EOC) to the host processor. EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and remains low until the conversion is complete and the data is ready for transfer.
GND 10 — Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.
I/O CLOCK 18 I

Input /output clock. I/O CLOCK receives the serial input and performs the following four functions:

  1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK with the multiplexer address available after the fourth rising edge.
  2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input begins charging the capacitor array and continues to do so until the last falling edge of I/O CLOCK.
  3. The remaining 11 bits of the previous conversion data are shifted out on DATA OUT. Data changes on the falling edge of I/O CLOCK.
  4. Control of the conversion is transferred to the internal state controller on the falling edge of the last I/O CLOCK.
REF+ 14 I/O Positive reference voltage The upper reference voltage value (nominally VCC) is applied to REF+. The maximum analog input voltage range is determined by the difference between the voltage applied to terminals REF+ and REF–.
REF– 13 I/O Negative reference voltage. The lower reference voltage value (nominally ground) is applied to REF–. This pin is connected to analog ground (GND of the ADC) when internal reference is used.
VCC 20 — Positive supply voltage
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