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SLAS354C September 2001 – September 2015 TLV2553

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

DW|20
- MPDS173B
PW|20
- MPDS362A

散热焊盘机械数据 (封装 | 引脚)

订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_CC	Supply voltage⁽²⁾	–0.5	6.5	V
V_I	Input voltage (any input)	–0.3	V_CC + 0.3
V_O	Output voltage	–0.3	V_CC + 0.3
V_ref+	Positive reference voltage	–0.3	V_CC + 0.3
V_ref–	Negative reference voltage	–0.3	V_CC + 0.3
I_I	Peak input current (any input)	–20	20	mA
	Peak total input current (all inputs)	–30	30	mA
T_J	Operating virtual junction temperature	–40	150	°C
T_A	Operating free-air temperature	–40	85
T_stg	Storage temperature	–65	150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the GND terminal with REF– and GND wired together (unless otherwise noted).

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

				MIN	NOM	MAX	UNIT
V_CC	Supply voltage			2.7		5.5	V
	I/O CLOCK frequency	V_CC = 4.5 V to 5.5 V	16-bit I/O	0.01		15	MHz
			12-bit I/O	0.01		15
			8-bit I/O	0.01		15
		V_CC = 2.7 V to 3.6 V		0.01		10
I/O CLOCK	Tolerable clock jitter	V_CC = 4.5 V to 5.5 V				0.38	ns
	Aperature jitter	V_CC = 4.5 V to 5.5 V			100		ps
	Analog input voltage⁽¹⁾	V_CC = 4.5 V to 5.5 V		0		(REF+ ) – (REF– )	V
		V_CC = 3 V to 3.6 V		0		(REF+ ) – (REF– )
		V_CC = 2.7 V to 3 V		0		(REF+ ) – (REF– )
V_IH	High-level control input voltage	V_CC = 4.5 V to 5.5 V		2			V
V_IH	High-level control input voltage	V_CC = 2.7 V to 3.6 V		2.1			V
V_IL	Low-level control input voltage	V_CC = 4.5 V to 5.5 V				0.8	V
V_IL	Low-level control input voltage	V_CC = 2.7 V to 3.6 V				0.6	V
T_A	Operating free-air temperature	TLV2553I		–40		85	°C

(1) Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than the voltage applied to REF– convert as all zeros (000000000000).

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TLV2553		UNIT
		DW (SOIC)	PW (TSSOP)
		20 PINS	20 PINS
R_θJA	Junction-to-ambient thermal resistance	66	88.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	31.4	21.6	°C/W
R_θJB	Junction-to-board thermal resistance	33.7	40.4	°C/W
ψ_JT	Junction-to-top characterization parameter	7.4	0.8	°C/W
ψ_JB	Junction-to-board characterization parameter	33.3	39.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over recommended operating free-air temperature range, when V_CC = 5 V: V_REF+ = 5 V, I/O CLOCK frequency = 15 MHz, when V_CC = 2.7 V: V_REF+ = 2.5 V, I/O CLOCK frequency = 10 MHz (unless otherwise noted)

PARAMETER			TEST CONDITIONS			MIN	TYP⁽¹⁾	MAX	UNIT
V_OH	High-level output voltage		V_CC = 4.5 V, I_OH = –1.6 mA V_CC = 2.7 V, I_OH = –0.2 mA		30 pF	2.4			V
V_OH	High-level output voltage		V_CC = 4.5 V, I_OH = –20 μA V_CC = 2.7 V, I_OH = –20 μA		30 pF	V_CC – 0.1			V
V_OL	Low-level output voltage		V_CC = 4.5 V, I_OL = –1.6 mA V_CC = 2.7 V, I_OL = –0.8 mA		30 pF			0.4	V
V_OL	Low-level output voltage		V_CC = 4.5 V, I_OL = –20 μA V_CC = 2.7 V, I_OL = –20 μA		30 pF			0.1	V
I_OZ	High-impedance off-state output current		V_O = V_CC, CS = V_CC				1	2.5	μA
I_OZ	High-impedance off-state output current		V_O = 0 V, CS = V_CC				–1	–2.5	μA
I_CC	Operating supply current		CS = 0 V, External reference	V_CC = 5 V				1.2	mA
I_CC	Operating supply current		CS = 0 V, External reference	V_CC = 2.7 V				0.9	mA
I_CC(PD)	Power-down current		For all digital inputs, 0 ≤ V_I ≤ 0.5 V or V_I ≥ V_CC – 0.5 V, I/O CLOCK = 0 V	Software power down			0.1	1	μA
I_CC(PD)	Power-down current			Auto power down			0.1	10	μA
I_IH	High-level input current		V_I = V_CC				0.005	2.5	μA
I_IL	Low-level input current		V_I = 0 V				–0.005	–2.5	μA
I_lkg	Selected channel leakage current		Selected channel at V_CC , Unselected channel at 0 V					1	μA
I_lkg	Selected channel leakage current		Selected channel at 0 V, Unselected channel at V_CC					–1	μA
f_OSC	Internal oscillator frequency		V_CC = 4.5 V to 5.5 V			3.27			MHz
f_OSC	Internal oscillator frequency		V_CC = 2.7 V to 3.6 V			2.56			MHz
t_convert	Conversion time (13.5 × (1/f_OSC) + 25 ns)		V_CC = 4.5 V to 5.5 V					4.15	μs
t_convert	Conversion time (13.5 × (1/f_OSC) + 25 ns)		V_CC = 2.7 V to 3.6 V					5.54	μs
	Internal oscillator frequency voltage					3.6		4.1	V
Z_i	Input impedance⁽²⁾	Analog inputs	V_CC = 4.5 V					500	Ω
Z_i	Input impedance⁽²⁾	Analog inputs	V_CC = 2.7 V					600	Ω
C_i	Input capacitance	Analog inputs					45	55	pF
C_i	Input capacitance	Control inputs					5	15	pF

(1) All typical values are at V_CC = 5 V, T_A = 25°C.

(2) The switch resistance is very nonlinear and varies with input voltage and supply voltage. This is the worst case.

6.6 External Reference Specifications

PARAMETER		TEST CONDITIONS		MIN	TYP⁽¹⁾	MAX	UNIT
REF–	Reference input voltage	V_CC = 4.5 V to 5.5 V		–0.1	0	0.1	V
REF–	Reference input voltage	V_CC = 2.7 V to 3.6 V		–0.1	0	0.1	V
REF+	Reference input voltage	V_CC = 4.5 V to 5.5 V		2		V_CC	V
REF+	Reference input voltage	V_CC = 2.7 V to 3.6 V		2		V_CC	V
	External reference input voltage difference, (REF+) – (REF–)⁽²⁾	V_CC = 4.5 V to 5.5 V		1.9		V_CC	V
		V_CC = 2.7 V to 3.6 V		1.9		V_CC	V
	External reference supply current	CS at 0 V	V_CC = 4.5 V to 5.5 V			0.94	mA
	External reference supply current	CS at 0 V	V_CC = 2.7 V to 3.6 V			0.62	mA
	Reference input impedance	V_CC = 5 V	Static	1			MΩ
		V_CC = 5 V	During sampling/conversion	6		9	kΩ
		V_CC = 2.7 V	Static	1			MΩ
		V_CC = 2.7 V	During sampling/conversion	6		9	kΩ

(1) All typical values are at T_A = 25°C.

(2) Add a 0.1-µF capacitor between REF+ and REF– pins when external reference is used.

6.7 Operating Characteristics

over recommended operating free-air temperature range, V_REF+ = 5 V, I/O CLOCK frequency = 15 MHz when V_CC = 5 V, V_REF+ = 2.5 V, I/O CLOCK frequency = 10 MHz when V_CC = 2.7 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
INL	Integral linearity error⁽³⁾		–1		1	LSB
DNL	Differential linearity error		–1		1	LSB
E_O	Offset error⁽⁴⁾	See ⁽²⁾	–2		2	mV
E_Q	Gain error⁽⁴⁾	See⁽²⁾	–3		3	mV
E_T	Total unadjusted error⁽⁵⁾			±15		LSB
	Self-test output code Table 2, ⁽⁶⁾	Address data input = 1011		2048
		Address data input = 1100		0
		Address data input = 1101		4095

(1) All typical values are at T_A = 25°C.

(2) Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than the voltage applied to REF– convert as all zeros (000000000000).

(3) Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.

(4) Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal midstep value at the offset point.

(5) Total unadjusted error comprises linearity, zero-scale, and full-scale errors.

(6) Both the input address and the output codes are expressed in positive logic.

6.8 Timing Requirements: V_REF+ = 5 V

over recommended operating free-air temperature range, I/O CLOCK frequency = 15 MHz, V_CC = 5 V, load = 25 pF (unless otherwise noted)

			MIN	MAX	UNIT
t_w1	Pulse duration I/O CLOCK high or low		26.7	100000	ns
t_su1	Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 32)		12		ns
t_h1	Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 32)		0		ns
t_su2	Setup time CS low before first rising I/O CLOCK edge⁽¹⁾ (see Figure 33)		25		ns
t_h2	Hold time CS pulse duration high time (see Figure 33)		100		ns
t_h3	Hold time CS low after last I/O CLOCK falling edge (see Figure 33)		0		ns
t_h4	Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 34)		2		ns
t_h5	Hold time CS high after EOC rising edge when CS is toggled (see Figure 37)		0		ns
t_d1	Delay time CS falling edge to DATA OUT valid (MSB or LSB) (see Figure 31)	Load = 25 pF		28	ns
t_d1		Load = 10 pF		20	ns
t_d2	Delay time CS rising edge to DATA OUT high impedance (see Figure 31)			10	ns
t_d3	Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 34)		2	20	ns
t_d4	Delay time Last I/O CLOCK falling edge to EOC falling edge			55	ns
t_d5	Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion			1.5	µs
t_t1	Transition time I/O CLOCK ⁽¹⁾(see Figure 34)			1	µs
t_t2	Transition time DATA OUT (see Figure 34)			5	ns
t_t3	Transition time INT/EOC, C_L at 7 pF (see Figure 36)			2.4	ns
t_t4	Transition time DATA IN, CS			10	µs
t_cycle	Total cycle time (sample, conversion and delays)⁽¹⁾			MAX(t_convert) + I/O period (8/12/16 CLKs)	µs
t_sample	Channel acquisition time (sample), at 1 kΩ,⁽¹⁾ (See Figure 1 through Figure 6)	Source impedance = 25 Ω	600		ns
		Source impedance = 100 Ω	650
		Source impedance = 500 Ω	700
		Source impedance = 1 kΩ	1000

(1) I/O CLOCK period = 8X [1/(I/O CLOCK frequency)] or 12X [1/(I/O CLOCK frequency)] or 16X [1/(I/O CLOCK frequency)] depends on I/O format selected.

6.9 Timing Requirements: V_REF+ = 2.5 V

over recommended operating free-air temperature range, I/O CLOCK frequency = 10 MHz, V_CC = 2.7 V, load = 25 pF (unless otherwise noted)

			MIN	MAX	UNIT
t_w1	Pulse duration I/O CLOCK high or low		40	100000	ns
t_su1	Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 32)		22		ns
t_h1	Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 32)		0		ns
t_su2	Setup time CS low before first rising I/O CLOCK edge⁽¹⁾ (see Figure 33)		33		ns
t_h2	Hold time CS pulse duration high time (see Figure 33)		100		ns
t_h3	Hold time CS low after last I/O CLOCK falling edge (see Figure 33)		0		ns
t_h4	Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 33)		2		ns
t_h5	Hold time CS high after EOC rising edge when CS is toggled (see Figure 37)		0		ns
t_d1	Delay time CS falling edge to DATA OUT valid (MSB or LSB) (see Figure 31)	Load = 25 pF		30	ns
t_d1		Load = 10 pF		22	ns
t_d2	Delay time CS rising edge to DATA OUT high impedance (see Figure 31)			10	ns
t_d3	Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 34)		2	33	ns
t_d4	Delay time Last I/O CLOCK falling edge to EOC falling edge			75	ns
t_d5	Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion			1.5	µs
t_t1	Transition time I/O CLOCK ⁽¹⁾(see Figure 34)			1	µs
t_t2	Transition time DATA OUT (see Figure 34)			5	ns
t_t3	Transition time INT/EOC, C_L at 7 pF (see Figure 36)			4	ns
t_t4	Transition time DATA IN, CS			10	µs
t_cycle	Total cycle time (sample, conversion and delays)⁽¹⁾			MAX(t_convert) + I/O period (8/12/16 CLKs)	µs
t_sample	Channel acquisition time (sample), at 1 kΩ,⁽¹⁾ (See Figure 1 through Figure 6)	Source impedance = 25 Ω	800		ns
		Source impedance = 100 Ω	850
		Source impedance = 500 Ω	1000
		Source impedance = 1 kΩ	1600

(1) I/O CLOCK period = 8X [1/(I/O CLOCK frequency)] or 12X [1/(I/O CLOCK frequency)] or 16X [1/(I/O CLOCK frequency)] depends on I/O format selected.

Figure 1. Timing for 12-Clock Transfer Using CS With DATA OUT Set for MSB First

NOTE:

To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.

Figure 2. Timing for 12-Clock Transfer Not Using CS With DATA OUT Set for MSB First