9.2.2.1 Step 1

The system clock source (master clock) and the targeted ADC sampling frequency must be identified.

Depending on the targeted performance, the decimation filter type (A, B, or C) and AOSR value can be determined:

• Filter A must be used for 48-kHz high-performance operation; AOSR must be a multiple of 8
• Filter B must be used for up to 96-kHz operations; AOSR must be a multiple of 4
• Filter C must be used for up to 192-kHz operations; AOSR must be a multiple of 2

In all cases, Equation 6 limits the AOSR range:

Based on the identified filter type and the required signal-processing capabilities, the appropriate processing block can be determined from the list of available processing blocks (PRB_R1 to PRB_R18).

Based on the available master clock, the chosen AOSR and the targeted sampling rate, the clock divider values NADC and MADC can be determined. If necessary, the internal PLL can add a large degree of flexibility.

Equation 7 describes that, in summary, ADC_CLKIN (derived directly from the system clock source or from the internal PLL) divided by MADC, NADC, and AOSR must be equal to the ADC sampling rate ADC_fs. The ADC_CLKIN clock signal is shared with the DAC clock-generation block.

To a large degree, NADC and MADC can be chosen independently in the range of 1 to 128. In general, as long as Equation 8 is met, NADC must be as large as possible:

RC is a function of the chosen processing block and is listed in Table 6.

The common-mode voltage setting of the device is determined by the available analog power supply.

At this point, the PRB_Rx, AOSR, NADC, MADC, and input and output common-mode values device-specific parameters are known. If the PLL is used, the PLL parameters P, J, D, and R are determined as well.