8.3.5 Digital Audio Data Serial Interface

Audio data are transferred between the host processor and the TLV320ADC3100 via the digital-audio serial-data interface, or audio bus. The audio bus on this device is flexible, including left- or right-justified data options, support for I²S or pulse code modulation (PCM) protocols, programmable data-length options, a time-division multiplexing (TDM) mode for multichannel operation, flexible master and slave configurability for each bus clock line, and the ability to directly communicate with multiple devices within a system.

The audio serial interface on the TLV320ADC3100 has an extensive I/O control for communication with two independent processors for audio data. The processors can communicate with the device one at a time. This feature is enabled by register programming of the various pin selections.

The audio bus of the TLV320ADC3100 can be configured for left- or right-justified, I²S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with the data width programmable in 16, 20, 24, or 32 bits by configuring page 0, register 27, bits 5:4. In addition, the word clock and bit clock can be independently configured in either master or slave mode for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and can be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum-selected ADC sampling frequency.

The bit clock is used to clock in and out the digital audio data across the serial bus. When in master mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in page 0, register 30; see Figure 27. Accommodating various word lengths as well as supporting the case when multiple TLV320ADC3100s share the same audio bus may require that the number of bit-clock pulses in a frame be adjusted.

The TLV320ADC3100 also includes a feature to offset the position of the start of a data transfer with respect to the word clock. There are two configurations that allow using either a single offset for both channels or to use separate offsets. The Ch_Offset_1 reference represents the value in page 0, register 28 and Ch_Offset_2 represents the value in page 0, register 37. When page 0, register 38, bit 0 is set to zero (time-slot-based channel assignment is disabled), the offset of both channels is controlled, in terms of number of bit clocks, by the programming in page 0, register 28 (Ch_Offset_1). When page 0, register 38, bit 0 = 1 (time-slot-based channel assignment enabled), the first channel is controlled, in terms of number of bit clocks, by the programming in page 0, register 28 (Ch_Offset_1), and the second channel is controlled, in terms of number of bit clocks, by the programming in page 0, register 37 (Ch_Offset_2), where register 37 programs the delay between the first word and the second word. Also, the relative order of the two channels can be swapped, depending on the programmable register bit (page 0, register 38, bit 4) that enables swapping of the channels.

The TLV320ADC3100 also supports a feature for inverting the bit clock polarity used for transferring the audio data as compared to the default clock polarity used. This feature can be used independently of the audio interface mode chosen. The bit clock polarity can be configured by writing to page 0, register 29, bit 3.

The TLV320ADC3100 further includes programmability (page 0, register 27, bit 0) to place DOUT in the high-impedance state at the end of data transfer (that is, at the end of the bit cycle corresponding to the LSB of a channel). By combining this capability with the ability to program at what bit clock in a frame the audio data begins, TDM can be accomplished, resulting in multiple ADCs able to use a single audio serial data bus. To further enhance the tri-state capability, the TLV320ADC3100 can be put in a high-impedance state a half bit cycle earlier by setting page 0, register 38, bit 1 to 1. When the audio serial data bus is powered down while configured in master mode, the pins associated with the interface are put into a high-impedance output state.

Either or both of the two channels can be disabled in LJF, I²S, and DSP modes by using page 0, register 38, bits 3:2. Figure 10 shows the interface timing when both channels are enabled and early tri-stating is enabled. Figure 11 shows the effect of setting page 0, register 38, bit 2, first channel disabled, and setting page 0, register 27, bit 0 to 1, which enables placing DOUT in the high-impedance state. If placing DOUT in the high-impedance state is disabled, then the DOUT signal is driven to logic level 0.

Figure 10. Both Channels Enabled, Early Tri-Stating Enabled

Figure 11. First Channel Disabled, Second Channel Enabled, Tri-Stating Enabled

The sync signal for the ADC filter is not generated based on the disabled channel. The sync signal for the filter corresponds to the beginning of the earlier of the two channels. If the first channel is disabled, the filter sync is generated at the beginning of the second channel, if enabled. If both channels are disabled, there is no output to the serial bus, and the filter sync corresponds to the beginning of the frame.

By default, when the word clocks and bit clocks are generated by the TLV320ADC3100, these clocks are active only when the ADC is powered up within the device. This internal clock gating is done to save power. However, the internal clock gating architecture also supports a feature wherein both the word clocks and bit clocks can be active even when the codec in the device is powered down. This feature is useful when using the TDM mode with multiple codecs on the same bus or when word clocks or bit clocks are used in the same system as general-purpose clocks.