8.3.5.3 I²S Mode

In I²S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock. Figure 19 shows the standard I²S timing.

Figure 19. I²S Mode (Standard Timing)

Figure 20 shows the I²S mode timing with Ch_Offset_1 = 2.

Figure 20. I²S Mode With Ch_Offset_1 = 2

Figure 21 shows the I²S mode timing with Ch_Offset_1 = 0 and the bit clock inverted.

Figure 21. I²S Mode With Ch_Offset_1 = 0, Bit Clock Inverted

For the I²S mode, the number of bit clocks per channel must be greater than or equal to the programmed word length of the data. Also, the programmed offset value must be less than the number of bit clocks per frame by at least the programmed word length of the data.