8.3.5.4 DSP Mode

In DSP mode, the rising edge of the word clock starts the data transfer with the left-channel data first and is immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock. Figure 22 shows the standard timing for the DSP mode.

Figure 22. DSP Mode (Standard Timing)

Figure 23 shows the DSP mode timing with Ch_Offset_1 = 1.

Figure 23. DSP Mode With Ch_Offset_1 = 1

Figure 24 shows the DSP mode timing with Ch_Offset_1 = 0 and the bit clock inverted.

Figure 24. DSP Mode With Ch_Offset_1 = 0, Bit Clock Inverted

For DSP mode, the number of bit clocks per frame must be greater than twice the programmed word length of the data. Also, the programmed offset value must be less than the number of bit clocks per frame by at least the programmed word length of the data.

Figure 25 shows the DSP time-slot-based mode without channel swapping, and with Ch_Offset_1 = 0 and Ch_Offset_2 = 3. The MSB of the left channel data is valid on the first falling edge of the bit clock after the rising edge of the word clock. Because the right channel has an offset of 3, the MSB of its data is valid on the third falling edge of the bit clock after the LSB of the left-channel data. As in the case of other modes, the serial output bus is put in the high-impedance state, if tri-stating of the output is enabled, during all extra bit-clock cycles in the frame.

Figure 25. DSP Mode, Time-Slot-Based Mode Enabled, Ch_Offset_1 = 0, Ch_Offset_2 = 3

Figure 26 shows the timing diagram for the DSP mode with left and right channels swapped, Ch_Offset_1 = 0, and Ch_Offset_2 = 3. The MSB of the right channel is valid on the first falling edge of the bit clock after the rising edge of the word clock. Similarly, the MSB of the left channel is valid three bit-clock cycles after the LSB of right channel because the offset for the left channel is 3.

Figure 26. DSP Mode, Time-Slot-Based Mode Enabled, Ch_Offset_1 = 0, Ch_Offset_2 = 3, Channel Swap Enabled