ZHCSHY2 March   2018 TLV320ADC3100

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      功能方框图
  4. 修订历史记录
  5. 说明 (续)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2S, LJF, RJF Timing in Master Mode
    7. 7.7  Timing Requirements: DSP Timing in Master Mode
    8. 7.8  Timing Requirements: I2S, LJF, RJF Timing in Slave Mode
    9. 7.9  Timing Requirements: DSP Timing in Slave Mode
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Hardware Reset
      2. 8.3.2  PLL Start-up
      3. 8.3.3  Software Power Down
      4. 8.3.4  Audio Data Converters
      5. 8.3.5  Digital Audio Data Serial Interface
        1. 8.3.5.1 Right-Justified Mode
        2. 8.3.5.2 Left-Justified Mode
        3. 8.3.5.3 I2S Mode
        4. 8.3.5.4 DSP Mode
      6. 8.3.6  Audio Clock Generation
      7. 8.3.7  Stereo Audio ADC
      8. 8.3.8  Audio Analog Inputs
        1. 8.3.8.1 Digital Volume Control
        2. 8.3.8.2 Fine Digital Gain Adjustment
        3. 8.3.8.3 AGC
      9. 8.3.9  Input Impedance and VCM Control
      10. 8.3.10 MICBIAS Generation
      11. 8.3.11 ADC Decimation Filtering and Signal Processing
        1. 8.3.11.1 Processing Blocks
        2. 8.3.11.2 Processing Blocks: Details
        3. 8.3.11.3 User-Programmable Filters
          1. 8.3.11.3.1 First-Order IIR Section
          2. 8.3.11.3.2 Biquad Section
          3. 8.3.11.3.3 FIR Section
        4. 8.3.11.4 Decimation Filter
          1. 8.3.11.4.1 Decimation Filter A
          2. 8.3.11.4.2 Decimation Filter B
          3. 8.3.11.4.3 Decimation Filter C
        5. 8.3.11.5 ADC Data Interface
      12. 8.3.12 TLV320ADC3100 Comparison
    4. 8.4 Device Functional Modes
      1. 8.4.1 Recording Mode
    5. 8.5 Programming
      1. 8.5.1 Digital Control Serial Interface
        1. 8.5.1.1 I2C Control Mode
    6. 8.6 Register Maps
      1. 8.6.1 Control Registers
      2. 8.6.2 Control Registers, Page 0: Clock Multipliers and Dividers, Serial Interfaces, Flags, Interrupts and Programming of GPIOs
        1. 8.6.2.1  Register 0: Page Control Register (address = 0d) [reset = 0000 0000b], Page 0
          1. Table 17. Register 0: Page Control Register Field Descriptions
        2. 8.6.2.2  Register 1: Software Reset (address = 01d) [reset = 00h], Page 0
          1. Table 18. Register 1: Software Reset Field Descriptions
        3. 8.6.2.3  Register 2: Reserved (address = 02d) [reset = 00h], Page 0
          1. Table 19. Register 2: Reserved Field Descriptions
        4. 8.6.2.4  Register 3: Reserved (address = 03d) [reset = XXh], Page 0
          1. Table 20. Register 3: Reserved Field Descriptions
        5. 8.6.2.5  Register 4: Clock-Gen Multiplexing (address = 04d) [reset = 00h], Page 0
          1. Table 21. Register 4: Clock-Gen Multiplexing Field Descriptions
        6. 8.6.2.6  Register 5: PLL P and R-VAL (address = 05d) [reset = 11h], Page 0
          1. Table 22. Register 5: PLL P and R-VAL Field Descriptions
        7. 8.6.2.7  Register 6: PLL J-VAL (address = 06d) [reset = 0000 0100b], Page 0
          1. Table 23. Register 6: PLL J-VAL Field Descriptions
        8. 8.6.2.8  Register 7: PLL D-VAL MSB (address = 07d) [reset = 00h], Page 0
          1. Table 24. Register 7: PLL D-VAL MSB Field Descriptions
        9. 8.6.2.9  Register 8: PLL D-VAL LSB (address = 08d) [reset = 00h], Page 0
          1. Table 25. Register 8: PLL D-VAL LSB Field Descriptions
        10. 8.6.2.10 Registers 9–17: Reserved (addresses = 09d, 10d, 11d, 12d, 13d, 14d, 15d, 16d, 17d) [reset = XXh], Page 0
          1. Table 26. Registers 9–17: Reserved Field Descriptions
        11. 8.6.2.11 Register 18: ADC NADC Clock Divider (address = 18d) [reset = 0000 0001b], Page 0
          1. Table 27. Register 18: ADC NADC Clock Divider Field Descriptions
        12. 8.6.2.12 Register 19: ADC MADC Clock Divider (address = 19d) [reset = 0000 0001b], Page 0
          1. Table 28. Register 19: ADC MADC Clock Divider Field Descriptions
        13. 8.6.2.13 Register 20: ADC AOSR (address = 20d) [reset = 1000  0000b], Page 0
          1. Table 29. Register 20: ADC AOSR Field Descriptions
        14. 8.6.2.14 Register 21: ADC IADC (address = 21d) [reset = 1000  0000b], Page 0
          1. Table 30. Register 21: ADC IADC Field Descriptions
        15. 8.6.2.15 Register 22: ADC Digital Filter Engine Decimation (address = 22d) [reset = 0000 0100b], Page 0
          1. Table 31. Register 22: ADC Digital Filter Engine Decimation Field Descriptions
        16. 8.6.2.16 Registers 23–24 (addresses) = 23d, 24d) [reset = XXh], Page 0
          1. Table 32. Registers 23–24 Field Descriptions
        17. 8.6.2.17 Register 25: CLKOUT MUX (address = 25d) [reset = 00h], Page 0
          1. Table 33. Register 25: CLKOUT MUX Field Descriptions
        18. 8.6.2.18 Register 26: CLKOUT M Divider (address = 26d) [reset = 0000 0001b], Page 0
          1. Table 34. Register 26: CLKOUT M Divider Field Descriptions
        19. 8.6.2.19 Register 27: ADC Audio Interface Control 1 (address = 27d) [reset = 00h], Page 0
          1. Table 35. Register 27: ADC Audio Interface Control 1 Field Descriptions
        20. 8.6.2.20 Register 28: Data Slot Offset Programmability 1 (Ch_Offset_1) (address = 28d) [reset = 00h], Page 0
          1. Table 36. Register 28: Data Slot Offset Programmability 1 (Ch_Offset_1) Field Descriptions
        21. 8.6.2.21 Register 29: ADC Interface Control 2 (address = 29d) [reset = 0000 0010b], Page 0
          1. Table 37. Register 29: ADC Interface Control 2 Field Descriptions
        22. 8.6.2.22 Register 30: BCLK N Divider (address = 30d) [reset = 0000 0001b], Page 0
          1. Table 38. Register 30: BCLK N Divider Field Descriptions
        23. 8.6.2.23 Register 31: Secondary Audio Interface Control 1 (address = 31d) [reset = 00h], Page 0
          1. Table 39. Register 31: Secondary Audio Interface Control 1 Field Descriptions
        24. 8.6.2.24 Register 32: Secondary Audio Interface Control 2 (address = 32d) [reset = 00h], Page 0
          1. Table 40. Register 32: Secondary Audio Interface Control 2 Field Descriptions
        25. 8.6.2.25 Register 33: Secondary Audio Interface Control 3 (address = 33d) [reset = 0001 0000b], Page 0
          1. Table 41. Register 33: Secondary Audio Interface Control 3 Field Descriptions
        26. 8.6.2.26 Register 34: I2S Sync (address = 34d) [reset = 00h], Page 0
          1. Table 42. Register 34: I2S Sync Field Descriptions
        27. 8.6.2.27 Register 35: Reserved (address = 35d) [reset = XXh], Page 0
          1. Table 43. Register 35: Reserved Field Descriptions
        28. 8.6.2.28 Register 36: ADC Flag Register (address = 36d) [reset = 00h], Page 0
          1. Table 44. Register 36: ADC Flag Register Field Descriptions
        29. 8.6.2.29 Register 37: Data Slot Offset Programmability 2 (Ch_Offset_2) (address = 37d) [reset = 00h], Page 0
          1. Table 45. Register 37: Data Slot Offset Programmability 2 (Ch_Offset_2) Field Descriptions
        30. 8.6.2.30 Register 38: I2S TDM Control Register (address = 38d) [reset = 0000 0010b], Page 0
          1. Table 46. Register 38: I2S TDM Control Register Field Descriptions
        31. 8.6.2.31 Registers 39–41 (addresses) = 39d, 40d, 41d) [reset = XXh], Page 0
          1. Table 47. Registers 39–41 Field Descriptions
        32. 8.6.2.32 Register 42: Interrupt Flags (Overflow) (address = 42d) [reset = 00h], Page 0
          1. Table 48. Register 42: Interrupt Flags (Overflow) Field Descriptions
        33. 8.6.2.33 Register 43: Interrupt Flags (Overflow) (address = 43d) [reset = 00h], Page 0
          1. Table 49. Register 43: Interrupt Flags (Overflow) Field Descriptions
        34. 8.6.2.34 Register 44: Reserved (address = 44d) [reset = XXh], Page 0
          1. Table 50. Register 44: Reserved Field Descriptions
        35. 8.6.2.35 Register 45: Interrupt Flags—ADC (address = 45d) [reset = 00h], Page 0
          1. Table 51. Register 45: Interrupt Flags—ADC Field Descriptions
        36. 8.6.2.36 Register 46: Reserved (address = 46d) [reset = XXh], Page 0
          1. Table 52. Register 46: Reserved Field Descriptions
        37. 8.6.2.37 Register 47: Interrupt Flags—ADC (address = 47d) [reset = 00h], Page 0
          1. Table 53. Register 47: Interrupt Flags—ADC Field Descriptions
        38. 8.6.2.38 Register 48: INT1 Interrupt Control (address = 48d) [reset = 00h], Page 0
          1. Table 54. Register 48: INT1 Interrupt Control Field Descriptions
        39. 8.6.2.39 Register 49: INT2 Interrupt Control (address = 49d) [reset = 00h], Page 0
          1. Table 55. Register 49: INT2 Interrupt Control Field Descriptions
        40. 8.6.2.40 Register 50: Reserved (address = 50d) [reset = XXh], Page 0
          1. Table 56. Register 50: Reserved Field Descriptions
        41. 8.6.2.41 Register 51: Reserved (address = 51d) [reset = 00h], Page 0
          1. Table 57. Register 51: Reserved
        42. 8.6.2.42 Register 52: GPIO1 Control (address = 52d) [reset = 00h], Page 0
          1. Table 58. Register 52: GPIO1 Control Field Descriptions
        43. 8.6.2.43 Register 53: DOUT (OUT Pin) Control (address = 53d) [reset = 0001 0010b], Page 0
          1. Table 59. Register 53: DOUT (OUT Pin) Control Field Descriptions
        44. 8.6.2.44 Registers 54–56 (addresses) = 54d, 55d, 56d) [reset = XXh], Page 0
          1. Table 60. Registers 54–56 Field Descriptions
        45. 8.6.2.45 Register 57: ADC Sync Control 1 (address = 57d) [reset = 00h], Page 0
          1. Table 61. Register 57: ADC Sync Control 1 Field Descriptions
        46. 8.6.2.46 Register 58: ADC Sync Control 2 (address = 58d) [reset = 00h], Page 0
          1. Table 62. Register 58: ADC Sync Control 2 Field Descriptions
        47. 8.6.2.47 Register 59: ADC CIC Filter Gain Control (address = 59d) [reset = 0100 0100h], Page 0
          1. Table 63. Register 59: ADC CIC Filter Gain Control Field Descriptions
        48. 8.6.2.48 Register 60: Reserved (address = 60d) [reset = 00h], Page 0
          1. Table 64. Register 60: Reserved Field Descriptions
        49. 8.6.2.49 Register 61: ADC Processing Block Selection (address = 61d) [reset = 0000 0001h], Page 0
          1. Table 65. Register 61: ADC Processing Block Selection Field Descriptions
        50. 8.6.2.50 Register 62: Programmable Instruction-Mode Control Bits (address = 62d) [reset = 00h], Page 0
          1. Table 66. Register 62: Reserved
        51. 8.6.2.51 Registers 63–79: Reserved (address = 63d - 79d) [reset = XXh], Page 0
          1. Table 67. Registers 63–79: Reserved Field Descriptions
        52. 8.6.2.52 Register 80: Reserved (address = 80d) [reset = 00h], Page 0
          1. Table 68. Register 80: Reserved
        53. 8.6.2.53 Register 81: ADC Digital (address = 81d) [reset = 00h], Page 0
          1. Table 69. Register 81: ADC Digital Field Descriptions
        54. 8.6.2.54 Register 82: ADC Fine Volume Control (address = 82d) [reset = 1000 1000h], Page 0
          1. Table 70. Register 82: ADC Fine Volume Control Field Descriptions
        55. 8.6.2.55 Register 83: Left ADC Volume Control (address = 83d) [reset = 00h], Page 0
          1. Table 71. Register 83: Left ADC Volume Control Field Descriptions
        56. 8.6.2.56 Register 84: Right ADC Volume Control (address = 84d) [reset = 00h], Page 0
          1. Table 72. Register 84: Right ADC Volume Control Field Descriptions
        57. 8.6.2.57 Register 85: Left ADC Phase Compensation (address = 85d) [reset = 00h], Page 0
          1. Table 73. Register 85: Left ADC Phase Compensation Field Descriptions
        58. 8.6.2.58 Register 86: Left AGC Control 1 (address = 86d) [reset = 00h], Page 0
          1. Table 74. Register 86: Left AGC Control 1 Field Descriptions
        59. 8.6.2.59 Register 87: Left AGC Control 2 (address = 87d) [reset = 00h], Page 0
          1. Table 75. Register 87: Left AGC Control 2 Field Descriptions
        60. 8.6.2.60 Register 88: Left AGC Maximum Gain (address = 88d) [reset = 0111 1111b], Page 0
          1. Table 76. Register 88: Left AGC Maximum Gain Field Descriptions
        61. 8.6.2.61 Register 89: Left AGC Attack Time (address = 89d) [reset = 00h], Page 0
          1. Table 77. Register 89: Left AGC Attack Time Field Descriptions
        62. 8.6.2.62 Register 90: Left AGC Decay Time (address = 90d) [reset = 00h], Page 0
          1. Table 78. Register 90: Left AGC Decay Time Field Descriptions
        63. 8.6.2.63 Register 91: Left AGC Noise Debounce (address = 91d) [reset = 00h], Page 0
          1. Table 79. Register 91: Left AGC Noise Debounce Field Descriptions
        64. 8.6.2.64 Register 92: Left AGC Signal Debounce (address = 92d) [reset = 00h], Page 0
          1. Table 80. Register 92: Left AGC Signal Debounce Field Descriptions
        65. 8.6.2.65 Register 93: Left AGC Gain Applied (address = 93d) [reset = 00h], Page 0
          1. Table 81. Register 93: Left AGC Gain Applied Field Descriptions
        66. 8.6.2.66 Register 94: Right AGC Control 1 (address = 94d) [reset = 00h], Page 0
          1. Table 82. Register 94: Right AGC Control 1 Field Descriptions
        67. 8.6.2.67 Register 95: Right AGC Control 2 (address = 95d) [reset = 00h], Page 0
          1. Table 83. Register 95: Right AGC Control 2 Field Descriptions
        68. 8.6.2.68 Register 96: Right AGC Maximum Gain (address = 96d) [reset = 0111 1111b], Page 0
          1. Table 84. Register 96: Right AGC Maximum Gain Field Descriptions
        69. 8.6.2.69 Register 97: Right AGC Attack Time (address = 97d) [reset = 00h], Page 0
          1. Table 85. Register 97: Right AGC Attack Time Field Descriptions
        70. 8.6.2.70 Register 98: Right AGC Decay Time (address = 98d) [reset = 00h], Page 0
          1. Table 86. Register 98: Right AGC Decay Time Field Descriptions
        71. 8.6.2.71 Register 99: Right AGC Noise Debounce (address = 99d) [reset = 00h], Page 0
          1. Table 87. Register 99: Right AGC Noise Debounce Field Descriptions
        72. 8.6.2.72 Register 100: Right AGC Signal Debounce (address = 100d) [reset = 00h], Page 0
          1. Table 88. Register 100: Right AGC Signal Debounce Field Descriptions
        73. 8.6.2.73 Register 101: Right AGC Gain Applied (address = 101d) [reset = 00h], Page 0
          1. Table 89. Register 101: Right AGC Gain Applied Field Descriptions
        74. 8.6.2.74 Register 102–127: Reserved (addresses) = 102d–127d) [reset = XXh], Page 0
          1. Table 90. Register 102–127: Reserved Field Descriptions
      3. 8.6.3 Control Registers, Page 1: ADC Routing, PGA, Power Controls, and So Forth
        1. 8.6.3.1  Register 0: Page Control Register (address = 0d) [reset = 00h], Page 1
          1. Table 91. Register 0: Page Control Register Field Descriptions
        2. 8.6.3.2  Register 1–25: Reserved (addresses) = 01d–25d) [reset = XXh], Page 1
          1. Table 92. Register 1–25: Reserved Field Descriptions
        3. 8.6.3.3  Register 26: Dither Control (address = 26d) [reset = 00h], Page 1
          1. Table 93. Register 26: Dither Control Field Descriptions
        4. 8.6.3.4  Register 27–50: Reserved (addresses) = 27d–50d) [reset = XXh], Page 1
          1. Table 94. Register 27–50: Reserved Field Descriptions
        5. 8.6.3.5  Register 51: MICBIAS Control (address = 51d) [reset = 00h], Page 1
          1. Table 95. Register 51: MICBIAS Control Field Descriptions
        6. 8.6.3.6  Register 52: Left ADC Input Selection for Left PGA (address = 52d) [reset = 0101 0111b], Page 1
          1. Table 96. Register 52: Left ADC Input Selection for Left PGA Field Descriptions
        7. 8.6.3.7  Register 53: Reserved (address = 53d) [reset = XXh], Page 1
          1. Table 97. Register 53: Reserved Field Descriptions
        8. 8.6.3.8  Register 54: Left ADC Input Selection for Left PGA (address = 54d) [reset = 0011 1111h], Page 1
          1. Table 98. Register 54: Left ADC Input Selection for Left PGA Field Descriptions
        9. 8.6.3.9  Register 55: Right ADC Input Selection for Right PGA (address = 55d) [reset = 0101 0111b], Page 1
          1. Table 99. Register 55: Right ADC Input Selection for Right PGA Field Descriptions
        10. 8.6.3.10 Register 56: Reserved (address = 56d) [reset = XXh], Page 1
          1. Table 100. Register 56: Reserved Field Descriptions
        11. 8.6.3.11 Register 57: Right ADC Input Selection for Right PGA (address = 57d) [reset = 0001 0111b], Page 1
          1. Table 101. Register 57: Right ADC Input Selection for Right PGA Field Descriptions
        12. 8.6.3.12 Register 58: Reserved (address = 58d) [reset = XXh], Page 1
          1. Table 102. Register 58: Reserved Field Descriptions
        13. 8.6.3.13 Register 59: Left Analog PGA Settings (address = 59d) [reset = 1000 0000h], Page 1
          1. Table 103. Register 59: Left Analog PGA Settings Field Descriptions
        14. 8.6.3.14 Register 60: Right Analog PGA Settings (address = 60d) [reset = 1000 0000h], Page 1
          1. Table 104. Register 60: Right Analog PGA Settings Field Descriptions
        15. 8.6.3.15 Register 61: ADC Low Current Modes (address = 61d) [reset = 00h], Page 1
          1. Table 105. Register 61: ADC Low Current Modes Field Descriptions
        16. 8.6.3.16 Register 62: ADC Analog PGA Flags (address = 62d) [reset = 00h], Page 1
          1. Table 106. Register 62: ADC Analog PGA Flags Field Descriptions
        17. 8.6.3.17 Register 63–127: Reserved (addresses) = 63d–127d) [reset = XXh], Page 1
          1. Table 107. Register 63–127: Reserved Field Descriptions
      4. 8.6.4 Control Registers, Page 4: ADC Digital Filter Coefficients
        1. 8.6.4.1 Register 0: Page Control (address = 00d) [reset = 00h], Page 4
          1. Table 108. Register 0: Page Control Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Step 1
        2. 9.2.2.2 Step 2
        3. 9.2.2.3 Example Register Setup to Record Analog Data Through ADC to Digital Out
        4. 9.2.2.4 MICBIAS
        5. 9.2.2.5 Decoupling Capacitors
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

AGC

The TLV320ADC3100 includes automatic gain control (AGC) for ADC recording. AGC can be used to maintain a nominally constant output level when recording speech. As opposed to manually setting the PGA gain, in the AGC mode, the circuitry automatically adjusts the PGA gain as the input signal becomes overly loud or very weak, such as when a person speaking into a microphone moves closer to or farther from the microphone. The AGC algorithm has several programmable parameters (including target gain, attack and decay time constants, noise threshold, and maximum PGA applicable) that allow the algorithm to be fine-tuned for any particular application. The algorithm uses the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the nominal amplitude of the output signal. Because the gain can be changed at the sample interval time, the AGC algorithm operates at the ADC sample rate.

  • Target level represents the nominal output level at which the AGC attempts to hold the ADC output signal level. The TLV320ADC3100 allows programming of eight different target levels that can be programmed from –5.5 dB to –24 dB relative to a full-scale signal. Because the TLV320ADC3100 reacts to the signal absolute average and not to peak levels, TI recommends that the target level be set with enough margin to avoid clipping at the occurrence of loud sounds.
  • Attack time determines how quickly the AGC circuitry reduces the PGA gain when the output signal level exceeds the target level resulting from an increase in input signal level. A wide range of attack-time programmability is supported in terms of number of samples (that is, the number of ADC sample-frequency clock cycles).
  • Decay time determines how quickly the PGA gain is increased when the output signal level falls below the target level resulting from a reduction in input signal level. A wide range of decay-time programmability is supported in terms of number of samples (that is, the number of ADC sample-frequency clock cycles).
  • Noise threshold. If the input signal level falls below the noise threshold, the AGC considers the duration that the signal level remains below the threshold as silence, and thus brings down the gain to 0 dB in steps of 0.5 dB every sample period and sets the noise-threshold flag. The gain stays at 0 dB unless the input signal average rises above the noise threshold setting, thus preventing noise from being amplified in the absence of a signal. The noise threshold level in the AGC algorithm is programmable from –30 dB to –90 dB of full-scale. When the AGC noise threshold is set to –70 dB, –80 db, or –90 dB, the maximum applicable microphone input PGA setting must be greater than or equal to 11.5 dB, 21.5 dB, or 31.5 dB, respectively. This operation includes hysteresis and debounce to prevent the AGC gain from cycling between high gain and 0 dB when signals are near the noise threshold level. The noise (or silence) detection feature can also be entirely disabled.
  • Maximum applicable PGA allows the maximum gain applied by the AGC to be restricted. This restriction can be used for limiting PGA gain in situations where environmental noise is greater than the programmed noise threshold. Microphone input maximum PGA can be programmed from 0 dB to 40 dB in steps of 0.5 dB.
  • Hysteresis, as the name suggests, determines a window around the noise threshold that must be exceeded to detect if the recorded signal is indeed either noise or signal. If the energy of the recorded signal is initially greater than the noise threshold, then the AGC recognizes the signal as noise only when the energy of the recorded signal falls below the noise threshold by a value given by hysteresis. Similarly, after the recorded signal is recognized as noise, for the AGC to recognize the sound as a signal, its energy must exceed the noise threshold by a value given by the hysteresis setting. In order to prevent the AGC from jumping between noise and signal states (which can happen when the energy of the recorded signal is very close to the noise threshold), a non-zero hysteresis value must be chosen. The hysteresis feature can also be disabled.
  • Debounce time (noise and signal) determines the hysteresis in time domain for noise detection. The AGC continuously calculates the energy of the recorded signal. If the calculated energy is less than the set noise threshold, then the AGC does not increase the input gain to achieve the target level. However, to handle audible artifacts that can occur when the energy of the input signal is very close to the noise threshold, the AGC checks if the energy of the recorded signal is less than the noise threshold for a duration greater than the noise debounce time. Similarly, the AGC starts increasing the input-signal gain to reach the target level when the calculated energy of the input signal is greater than the noise threshold. Again, to avoid audible artifacts when the input-signal energy is very close to noise threshold, the energy of the input signal must continuously exceed the noise threshold value for the signal debounce time. If the debounce times are kept very small, then audible artifacts can result by rapidly enabling and disabling the AGC function. At the same time, if the debounce time is kept too large, then the AGC can take more time to respond to changes in input signal levels with respect to the noise threshold. Both noise and signal debounce time can be disabled.
  • The AGC noise threshold flag is a read-only flag indicating that the input signal has levels lower than the noise threshold, and thus is detected as noise (or silence). In such a condition, the AGC applies a gain of 0 dB.
  • Gain applied by the AGC is a read-only register setting that gives a real-time feedback to the system on the gain applied by the AGC to the recorded signal. This setting, along with the target setting, can be used to determine the input signal level. In a steady state situation:
     Target level (dB ) = gain applied by AGC (dB) + input signal level (dB)
    When the AGC noise threshold flag is set, then the status of the gain applied by the AGC is not valid.
  • The AGC saturation flag is a read-only flag indicating that the ADC output signal has not reached its target level. However, the AGC is unable to increase the gain further because the required gain is higher than the maximum allowed PGA gain. Such a situation can happen when the input signal has very low energy and the noise threshold is also set very low. When the AGC noise threshold flag is set, the status of the AGC saturation flag must be ignored.
  • The ADC saturation flag is a read-only flag indicating an overflow condition in the ADC channel. On overflow, the signal is clipped and distortion results. This distortion typically happens when the AGC target level is kept very high and the energy in the input signal increases faster than the attack time.
  • An AGC low-pass filter is used to help determine the average level of the input signal. This average level is compared to the programmed detection levels in the AGC to provide the correct functionality. This low-pass filter is in the form of a first-order IIR filter. Two 8-bit registers are used to form the 16-bit digital coefficient, as shown in the Register Maps section. In this way, a total of six registers are programmed to form the three IIR coefficients. Equation 2 shows how the transfer function of the filter is implemented for signal-level detection:
  • Equation 2. TLV320ADC3100 agclpf_las548.gif

    where

    • Coefficient N0 can be programmed by writing into page 4, registers 2 and 3
    • Coefficient N1 can be programmed by writing into page 4, registers 4 and 5
    • Coefficient D1 can be programmed by writing into page 4, registers 6 and 7
    • N0, N1, and D1 are 16-bit, 2s-complement numbers, and their default values implement a low-pass filter with cutoff at 0.002735 × ADC_fS

    Table 3 lists various AGC programming options. The AGC can be used only if the analog microphone input is routed to the ADC channel.

    Figure 28 illustrates the input and output signals along with the decay and attack times of the AGC.

    Table 3. AGC Parameter Settings

    FUNCTION CONTROL REGISTER
    LEFT ADC
    CONTROL REGISTER
    RIGHT ADC
    BIT
    AGC enable Page 0, register 86 Page 0, register 94 7
    Target level Page 0, register 86 Page 0, register 94 6:4
    Hysteresis Page 0, register 87 Page 0, register 95 7:6
    Noise threshold Page 0, register 87 Page 0, register 95 5:1
    Maximum applicable PGA Page 0, register 88 Page 0, register 96 6:0
    Time constants (attack time) Page 0, register 89 Page 0, register 97 7:0
    Time constants (decay time) Page 0, register 90 Page 0, register 98 7:0
    Debounce time (noise) Page 0, register 91 Page 0, register 99 4:0
    Debounce time (signal) Page 0, register 92 Page 0, register 100 3:0
    Gain applied by the AGC Page 0, register 93 Page 0, register 101 7:0 (read-only)
    AGC noise-threshold flag Page 0, register 45 (sticky flag),
    Page 0, register 47 (non-sticky flag)
    Page 0, register 45 (sticky flag),
    Page 0, register 47 (non-sticky flag)
    6:5 (read-only)
    AGC saturation flag Page 0, register 36 (sticky flag) Page 0, register 36 (sticky flag) 5, 1 (read-only)
    ADC saturation flag Page 0, register 42 (sticky flag),
    Page 0, register 43 (non-sticky flag)
    Page 0, register 42 (sticky flag),
    Page 0, register 43 (non-sticky flag)
    3:2 (read-only)
    TLV320ADC3100 agc_char_sbas906.gifFigure 28. AGC Characteristics

The TLV320ADC3100 includes two analog audio input pins, which can be configured as one fully-differential pair and one single-ended input, or as three single-ended audio inputs. These pins connect through series resistors and switches to the virtual ground terminals of two fully differential operational amplifiers (one per ADC and PGA channel). By selecting to turn on only one set of switches per operational amplifier at a time, the inputs can be effectively multiplexed to each ADC PGA channel.

By selecting to turn on multiple sets of switches per operational amplifier at a time, mixing can also be achieved. Mixing of multiple inputs can easily lead to PGA outputs that exceed the range of the internal operational amplifiers, resulting in saturation and clipping of the mixed output signal. Whenever mixing is being implemented, take adequate precautions to avoid such a saturation case from occurring. In general, the mixed signal must not exceed 2 VPP (single-ended) or 4 VPP (differential).

In most mixing applications, there is also a general requirement to adjust the levels of the individual signals being mixed. For example, if a soft signal and a large signal are to be mixed and played together, the soft signal generally must be amplified to a level comparable to the large signal before mixing. In order to accommodate this requirement, the TLV320ADC3100 includes an input level control on each of the individual inputs before they are mixed or multiplexed into the ADC PGAs, with programmable attenuation at 0 dB, –6 dB, or off.

NOTE

This input-level control is not intended to be a volume control, but instead used for coarse level setting. Finer soft-stepping of the input level is implemented in this device by the ADC PGA.

Figure 29 shows various available configurations for the audio input.

TLV320ADC3100 Audio_input_path_BAS906.gifFigure 29. TLV320ADC3100 Available Audio Input Path Configurations

Table 4 lists the available routing configurations for the audio signals on the TLV320ADC3100.

Table 4. TLV320ADC3100 Audio Signals

AUDIO SIGNALS AVAILABLE TO THE LEFT ADC AUDIO SIGNALS AVAILABLE TO THE RIGHT ADC
SINGLE-ENDED INPUTS DIFFERENTIAL INPUTS SINGLE-ENDED INPUTS DIFFERENTIAL INPUTS
IN2L(P) IN2L(P), IN3L(M) IN2R(P) IN2R(P), IN3R(M)
IN3L(M) IN2R(P), IN3R(M) IN3R(M) IN2L(P), IN3L(M)

Inputs can be selected as single-ended instead of fully differential, and mixing or multiplexing into the ADC PGAs is also possible in this mode. However, an input pair cannot be selected as fully differential for connection to one ADC PGA and simultaneously selected as single-ended for connection to the other ADC PGA channel. However, an input can be selected or mixed into both the left and right channel PGAs, as long as the PGA has the same configuration for both channels (either both single-ended or both fully differential).